nvme.h 文件参考

#include <rthw.h>
#include <rtthread.h>
#include <drivers/blk.h>

nvme.h 的引用(Include)关系图:

浏览该文件的源代码.

结构体
struct	rt_nvme_command_common
struct	rt_nvme_command_rw
struct	rt_nvme_command_identify
struct	rt_nvme_command_features
struct	rt_nvme_command_create_cq
struct	rt_nvme_command_create_sq
struct	rt_nvme_command_delete_queue
struct	rt_nvme_command_write_zeroes
struct	rt_nvme_command
struct	rt_nvme_completion
struct	rt_nvme_lba_format
struct	rt_nvme_queue
struct	rt_nvme_controller
struct	rt_nvme_device
struct	rt_nvme_ops

宏定义
#define	NVME_RSVD(offset, bytes_size)
#define	SGL_DESC_TYPE_DATA_BLOCK   0x0
#define	SGL_DESC_TYPE_BIT_BUCKET   0x1
#define	SGL_DESC_TYPE_SEGMENT   0x2
#define	SGL_DESC_TYPE_LAST_SEGMENT   0x3
#define	SGL_DESC_TYPE_KEYED_DATA_BLOCK   0x4
#define	SGL_DESC_TYPE_VENDOR_SPECIFIC   0xf
#define	RT_NVME_CAP_MQES(cap)
#define	RT_NVME_CAP_TIMEOUT(cap)
#define	RT_NVME_CAP_STRIDE(cap)
#define	RT_NVME_CAP_MPSMIN(cap)
#define	RT_NVME_CAP_MPSMAX(cap)
#define	RT_NVME_VS(major, minor)
#define	RT_NVME_AQ_DEPTH   32
#define	RT_NVME_NR_AEN_COMMANDS   1
#define	RT_NVME_AQ_BLK_MQ_DEPTH   (RT_NVME_AQ_DEPTH - RT_NVME_NR_AEN_COMMANDS)
#define	RT_NVME_AQ_MQ_TAG_DEPTH   (RT_NVME_AQ_BLK_MQ_DEPTH - 1)
#define	RT_NVME_ID_CTRATT_ELBAS   15 /* Extended LBA Formats Supported */
#define	RT_NVME_ID_CTRATT_DNVMS   14 /* Delete NVM Set */
#define	RT_NVME_ID_CTRATT_DEG   13 /* Delete Endurance Group */
#define	RT_NVME_ID_CTRATT_VCM   12 /* Variable Capacity Management */
#define	RT_NVME_ID_CTRATT_FCM   11 /* Fixed Capacity Management */
#define	RT_NVME_ID_CTRATT_MDS   10 /* Multi-Domain Subsystem */
#define	RT_NVME_ID_CTRATT_UUIDL   9 /* UUID List */
#define	RT_NVME_ID_CTRATT_SQA   8 /* SQ Associations */
#define	RT_NVME_ID_CTRATT_NG   7 /* Namespace Granularity */
#define	RT_NVME_ID_CTRATT_TBKAS   6 /* Traffic Based Keep Alive Support */
#define	RT_NVME_ID_CTRATT_PLM   5 /* Predictable Latency Mode */
#define	RT_NVME_ID_CTRATT_EG   4 /* Endurance Groups */
#define	RT_NVME_ID_CTRATT_RRL   3 /* Read Recovery Levels */
#define	RT_NVME_ID_CTRATT_NVMS   2 /* NVM Sets */
#define	RT_NVME_ID_CTRATT_NOPSPM   1 /* Non-Operational Power State Permissive Mode */
#define	RT_NVME_ID_CTRATT_HIS   0 /* Host Identifier Support */
#define	RT_NVME_ID_NVMSR_NVMEE   1 /* NVMe Enclosure */
#define	RT_NVME_ID_NVMSR_NVMESD   0 /* NVMe Storage Device */
#define	RT_NVME_ID_VWCI_VWCRV   7 /* VPD Write Cycles Remaining Valid */
#define	RT_NVME_ID_VWCI_VWCR   0 /* VPD Write Cycles Remaining */
#define	RT_NVME_ID_MEC_PCIEME   1 /* PCIe Port Management Endpoint */
#define	RT_NVME_ID_MEC_SMBUSME   0 /* SMBus/I2C Port Management Endpoint */
#define	RT_NVME_ID_FRMW_SMUD   5 /* Support Multiple Update Detection */
#define	RT_NVME_ID_FRMW_FAWR   4 /* Firmware Activation Without Reset */
#define	RT_NVME_ID_FRMW_NOFS   1 /* Number Of Firmware Slots */
#define	RT_NVME_ID_FRMW_FFSRO   0 /* First Firmware Slot Read Only */
#define	RT_NVME_ID_RPMBS_ASZ   24 /* Access Size */
#define	RT_NVME_ID_RPMBS_TSZ   16 /* Total Size */
#define	RT_NVME_ID_RPMBS_AM   3 /* Authentication Method */
#define	RT_NVME_ID_RPMBS_NORPMBU   2 /* Number of RPMB Units */
#define	RT_NVME_ID_SANICAP_NODMMAS   30 /* No-Deallocate Modifies Media After Sanitize */
#define	RT_NVME_ID_SANICAP_NDI   29 /* No-Deallocate Inhibited */
#define	RT_NVME_ID_SANICAP_OWS   2 /* Overwrite Support */
#define	RT_NVME_ID_SANICAP_BES   1 /* Block Erase Support */
#define	RT_NVME_ID_SANICAP_CES   0 /* Crypto Erase Support */
#define	RT_NVME_ID_SGL_SUPPORT_MASK   0x3
#define	RT_USING_NVME_QUEUE   (1 + (RT_USING_NVME_IO_QUEUE * RT_CPUS_NR))
#define	rt_disk_to_nvme_device(disk)

枚举
enum	{   RT_NVME_SC_SUCCESS = 0x0 , RT_NVME_SC_INVALID_OPCODE = 0x1 , RT_NVME_SC_INVALID_FIELD = 0x2 , RT_NVME_SC_CMDID_CONFLICT = 0x3 ,   RT_NVME_SC_DATA_XFER_ERROR = 0x4 , RT_NVME_SC_POWER_LOSS = 0x5 , RT_NVME_SC_INTERNAL = 0x6 , RT_NVME_SC_ABORT_REQ = 0x7 ,   RT_NVME_SC_ABORT_QUEUE = 0x8 , RT_NVME_SC_FUSED_FAIL = 0x9 , RT_NVME_SC_FUSED_MISSING = 0xa , RT_NVME_SC_INVALID_NS = 0xb ,   RT_NVME_SC_CMD_SEQ_ERROR = 0xc , RT_NVME_SC_SGL_INVALID_LAST = 0xd , RT_NVME_SC_SGL_INVALID_COUNT = 0xe , RT_NVME_SC_SGL_INVALID_DATA = 0xf ,   RT_NVME_SC_SGL_INVALID_METADATA = 0x10 , RT_NVME_SC_SGL_INVALID_TYPE = 0x11 , RT_NVME_SC_CMB_INVALID_USE = 0x12 , RT_NVME_SC_PRP_INVALID_OFFSET = 0x13 ,   RT_NVME_SC_ATOMIC_WU_EXCEEDED = 0x14 , RT_NVME_SC_OP_DENIED = 0x15 , RT_NVME_SC_SGL_INVALID_OFFSET = 0x16 , RT_NVME_SC_RESERVED = 0x17 ,   RT_NVME_SC_HOST_ID_INCONSIST = 0x18 , RT_NVME_SC_KA_TIMEOUT_EXPIRED = 0x19 , RT_NVME_SC_KA_TIMEOUT_INVALID = 0x1a , RT_NVME_SC_ABORTED_PREEMPT_ABORT = 0x1b ,   RT_NVME_SC_SANITIZE_FAILED = 0x1c , RT_NVME_SC_SANITIZE_IN_PROGRESS = 0x1d , RT_NVME_SC_SGL_INVALID_GRANULARITY = 0x1e , RT_NVME_SC_CMD_NOT_SUP_CMB_QUEUE = 0x1f ,   RT_NVME_SC_NS_WRITE_PROTECTED = 0x20 , RT_NVME_SC_CMD_INTERRUPTED = 0x21 , RT_NVME_SC_TRANSIENT_TR_ERR = 0x22 , RT_NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY = 0x24 ,   RT_NVME_SC_INVALID_IO_CMD_SET = 0x2c , RT_NVME_SC_LBA_RANGE = 0x80 , RT_NVME_SC_CAP_EXCEEDED = 0x81 , RT_NVME_SC_NS_NOT_READY = 0x82 ,   RT_NVME_SC_RESERVATION_CONFLICT = 0x83 , RT_NVME_SC_FORMAT_IN_PROGRESS = 0x84 , RT_NVME_SC_CQ_INVALID = 0x100 , RT_NVME_SC_QID_INVALID = 0x101 ,   RT_NVME_SC_QUEUE_SIZE = 0x102 , RT_NVME_SC_ABORT_LIMIT = 0x103 , RT_NVME_SC_ABORT_MISSING = 0x104 , RT_NVME_SC_ASYNC_LIMIT = 0x105 ,   RT_NVME_SC_FIRMWARE_SLOT = 0x106 , RT_NVME_SC_FIRMWARE_IMAGE = 0x107 , RT_NVME_SC_INVALID_VECTOR = 0x108 , RT_NVME_SC_INVALID_LOG_PAGE = 0x109 ,   RT_NVME_SC_INVALID_FORMAT = 0x10a , RT_NVME_SC_FW_NEEDS_CONV_RESET = 0x10b , RT_NVME_SC_INVALID_QUEUE = 0x10c , RT_NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d ,   RT_NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e , RT_NVME_SC_FEATURE_NOT_PER_NS = 0x10f , RT_NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110 , RT_NVME_SC_FW_NEEDS_RESET = 0x111 ,   RT_NVME_SC_FW_NEEDS_MAX_TIME = 0x112 , RT_NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113 , RT_NVME_SC_OVERLAPPING_RANGE = 0x114 , RT_NVME_SC_NS_INSUFFICIENT_CAP = 0x115 ,   RT_NVME_SC_NS_ID_UNAVAILABLE = 0x116 , RT_NVME_SC_NS_ALREADY_ATTACHED = 0x118 , RT_NVME_SC_NS_IS_PRIVATE = 0x119 , RT_NVME_SC_NS_NOT_ATTACHED = 0x11a ,   RT_NVME_SC_THIN_PROV_NOT_SUPP = 0x11b , RT_NVME_SC_CTRL_LIST_INVALID = 0x11c , RT_NVME_SC_SELT_TEST_IN_PROGRESS = 0x11d , RT_NVME_SC_BP_WRITE_PROHIBITED = 0x11e ,   RT_NVME_SC_CTRL_ID_INVALID = 0x11f , RT_NVME_SC_SEC_CTRL_STATE_INVALID = 0x120 , RT_NVME_SC_CTRL_RES_NUM_INVALID = 0x121 , RT_NVME_SC_RES_ID_INVALID = 0x122 ,   RT_NVME_SC_PMR_SAN_PROHIBITED = 0x123 , RT_NVME_SC_ANA_GROUP_ID_INVALID = 0x124 , RT_NVME_SC_ANA_ATTACH_FAILED = 0x125 , RT_NVME_SC_BAD_ATTRIBUTES = 0x180 ,   RT_NVME_SC_INVALID_PI = 0x181 , RT_NVME_SC_READ_ONLY = 0x182 , RT_NVME_SC_ONCS_NOT_SUPPORTED = 0x183 , RT_NVME_SC_CONNECT_FORMAT = 0x180 ,   RT_NVME_SC_CONNECT_CTRL_BUSY = 0x181 , RT_NVME_SC_CONNECT_INVALID_PARAM = 0x182 , RT_NVME_SC_CONNECT_RESTART_DISC = 0x183 , RT_NVME_SC_CONNECT_INVALID_HOST = 0x184 ,   RT_NVME_SC_DISCOVERY_RESTART = 0x190 , RT_NVME_SC_AUTH_REQUIRED = 0x191 , RT_NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8 , RT_NVME_SC_ZONE_FULL = 0x1b9 ,   RT_NVME_SC_ZONE_READ_ONLY = 0x1ba , RT_NVME_SC_ZONE_OFFLINE = 0x1bb , RT_NVME_SC_ZONE_INVALID_WRITE = 0x1bc , RT_NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd ,   RT_NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be , RT_NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf , RT_NVME_SC_WRITE_FAULT = 0x280 , RT_NVME_SC_READ_ERROR = 0x281 ,   RT_NVME_SC_GUARD_CHECK = 0x282 , RT_NVME_SC_APPTAG_CHECK = 0x283 , RT_NVME_SC_REFTAG_CHECK = 0x284 , RT_NVME_SC_COMPARE_FAILED = 0x285 ,   RT_NVME_SC_ACCESS_DENIED = 0x286 , RT_NVME_SC_UNWRITTEN_BLOCK = 0x287 , RT_NVME_SC_INTERNAL_PATH_ERROR = 0x300 , RT_NVME_SC_ANA_PERSISTENT_LOSS = 0x301 ,   RT_NVME_SC_ANA_INACCESSIBLE = 0x302 , RT_NVME_SC_ANA_TRANSITION = 0x303 , RT_NVME_SC_CTRL_PATH_ERROR = 0x360 , RT_NVME_SC_HOST_PATH_ERROR = 0x370 ,   RT_NVME_SC_HOST_ABORTED_CMD = 0x371 , RT_NVME_SC_CRD = 0x1800 , RT_NVME_SC_MORE = 0x2000 , RT_NVME_SC_DNR = 0x4000 }
enum	{   RT_NVME_ADMIN_OPCODE_DELETE_SQ = 0x00 , RT_NVME_ADMIN_OPCODE_CREATE_SQ = 0x01 , RT_NVME_ADMIN_OPCODE_GET_LOG_PAGE = 0x02 , RT_NVME_ADMIN_OPCODE_DELETE_CQ = 0x04 ,   RT_NVME_ADMIN_OPCODE_CREATE_CQ = 0x05 , RT_NVME_ADMIN_OPCODE_IDENTIFY = 0x06 , RT_NVME_ADMIN_OPCODE_ABORT_CMD = 0x08 , RT_NVME_ADMIN_OPCODE_SET_FEATURES = 0x09 ,   RT_NVME_ADMIN_OPCODE_GET_FEATURES = 0x0a , RT_NVME_ADMIN_OPCODE_ASYNC_EVENT = 0x0c , RT_NVME_ADMIN_OPCODE_NS_MGMT = 0x0d , RT_NVME_ADMIN_OPCODE_ACTIVATE_FW = 0x10 ,   RT_NVME_ADMIN_OPCODE_DOWNLOAD_FW = 0x11 , RT_NVME_ADMIN_OPCODE_DEV_SELF_TEST = 0x14 , RT_NVME_ADMIN_OPCODE_NS_ATTACH = 0x15 , RT_NVME_ADMIN_OPCODE_KEEP_ALIVE = 0x18 ,   RT_NVME_ADMIN_OPCODE_DIRECTIVE_SEND = 0x19 , RT_NVME_ADMIN_OPCODE_DIRECTIVE_RECV = 0x1a , RT_NVME_ADMIN_OPCODE_VIRTUAL_MGMT = 0x1c , RT_NVME_ADMIN_OPCODE_NVME_MI_SEND = 0x1d ,   RT_NVME_ADMIN_OPCODE_NVME_MI_RECV = 0x1e , RT_NVME_ADMIN_OPCODE_DBBUF = 0x7c , RT_NVME_ADMIN_OPCODE_FORMAT_NVM = 0x80 , RT_NVME_ADMIN_OPCODE_SECURITY_SEND = 0x81 ,   RT_NVME_ADMIN_OPCODE_SECURITY_RECV = 0x82 , RT_NVME_ADMIN_OPCODE_SANITIZE_NVM = 0x84 , RT_NVME_ADMIN_OPCODE_GET_LBA_STATUS = 0x86 , RT_NVME_ADMIN_OPCODE_VENDOR_START = 0xc0 }
enum	{   RT_NVME_CMD_FLUSH = 0x00 , RT_NVME_CMD_WRITE = 0x01 , RT_NVME_CMD_READ = 0x02 , RT_NVME_CMD_WRITE_UNCOR = 0x04 ,   RT_NVME_CMD_COMPARE = 0x05 , RT_NVME_CMD_WRITE_ZEROES = 0x08 , RT_NVME_CMD_DSM = 0x09 , RT_NVME_CMD_VERIFY = 0x0c ,   RT_NVME_CMD_RESV_REGISTER = 0x0d , RT_NVME_CMD_RESV_REPORT = 0x0e , RT_NVME_CMD_RESV_ACQUIRE = 0x11 , RT_NVME_CMD_RESV_RELEASE = 0x15 ,   RT_NVME_CMD_ZONE_MGMT_SEND = 0x79 , RT_NVME_CMD_ZONE_MGMT_RECV = 0x7a , RT_NVME_CMD_ZONE_APPEND = 0x7d , RT_NVME_CMD_VENDOR_START = 0x80 }
enum	{ RT_NVME_PSDT_PRP = 0x0 , RT_NVME_PSDT_SGL_MPTR_CONTIGUOUS = 0x1 , RT_NVME_PSDT_SGL_MPTR_SGL = 0x2 }
enum	{ RT_NVME_CMD_FLAGS_FUSE_SHIFT = 0x00 , RT_NVME_CMD_FLAGS_PSDT_SHIFT = 0x06 }
enum	{   RT_NVME_RW_LR = 1 << 15 , RT_NVME_RW_FUA = 1 << 14 , RT_NVME_RW_APPEND_PIREMAP = 1 << 9 , RT_NVME_RW_DSM_FREQ_UNSPEC = 0 ,   RT_NVME_RW_DSM_FREQ_TYPICAL = 1 , RT_NVME_RW_DSM_FREQ_RARE = 2 , RT_NVME_RW_DSM_FREQ_READS = 3 , RT_NVME_RW_DSM_FREQ_WRITES = 4 ,   RT_NVME_RW_DSM_FREQ_RW = 5 , RT_NVME_RW_DSM_FREQ_ONCE = 6 , RT_NVME_RW_DSM_FREQ_PREFETCH = 7 , RT_NVME_RW_DSM_FREQ_TEMP = 8 ,   RT_NVME_RW_DSM_LATENCY_NONE = 0 << 4 , RT_NVME_RW_DSM_LATENCY_IDLE = 1 << 4 , RT_NVME_RW_DSM_LATENCY_NORM = 2 << 4 , RT_NVME_RW_DSM_LATENCY_LOW = 3 << 4 ,   RT_NVME_RW_DSM_SEQ_REQ = 1 << 6 , RT_NVME_RW_DSM_COMPRESSED = 1 << 7 , RT_NVME_RW_PRINFO_PRCHK_REF = 1 << 10 , RT_NVME_RW_PRINFO_PRCHK_APP = 1 << 11 ,   RT_NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12 , RT_NVME_RW_PRINFO_PRACT = 1 << 13 , RT_NVME_RW_DTYPE_STREAMS = 1 << 4 , RT_NVME_WZ_DEAC = 1 << 9 }
enum	{   RT_NVME_QUEUE_PHYS_CONTIG = (1 << 0) , RT_NVME_CQ_IRQ_ENABLED = (1 << 1) , RT_NVME_SQ_PRIO_URGENT = (0 << 1) , RT_NVME_SQ_PRIO_HIGH = (1 << 1) ,   RT_NVME_SQ_PRIO_MEDIUM = (2 << 1) , RT_NVME_SQ_PRIO_LOW = (3 << 1) , RT_NVME_FEAT_ARBITRATION = 0x01 , RT_NVME_FEAT_POWER_MGMT = 0x02 ,   RT_NVME_FEAT_LBA_RANGE = 0x03 , RT_NVME_FEAT_TEMP_THRESH = 0x04 , RT_NVME_FEAT_ERR_RECOVERY = 0x05 , RT_NVME_FEAT_VOLATILE_WC = 0x06 ,   RT_NVME_FEAT_NUM_QUEUES = 0x07 , RT_NVME_FEAT_IRQ_COALESCE = 0x08 , RT_NVME_FEAT_IRQ_CONFIG = 0x09 , RT_NVME_FEAT_WRITE_ATOMIC = 0x0a ,   RT_NVME_FEAT_ASYNC_EVENT = 0x0b , RT_NVME_FEAT_AUTO_PST = 0x0c , RT_NVME_FEAT_SW_PROGRESS = 0x80 , RT_NVME_FEAT_HOST_ID = 0x81 ,   RT_NVME_FEAT_RESV_MASK = 0x82 , RT_NVME_FEAT_RESV_PERSIST = 0x83 , RT_NVME_LOG_ERROR = 0x01 , RT_NVME_LOG_SMART = 0x02 ,   RT_NVME_LOG_FW_SLOT = 0x03 , RT_NVME_LOG_RESERVATION = 0x80 , RT_NVME_FWACT_REPL = (0 << 3) , RT_NVME_FWACT_REPL_ACTV = (1 << 3) ,   RT_NVME_FWACT_ACTV = (2 << 3) }
enum	{   RT_NVME_REG_CAP = 0x0000 , RT_NVME_REG_VS = 0x0008 , RT_NVME_REG_INTMS = 0x000c , RT_NVME_REG_INTMC = 0x0010 ,   RT_NVME_REG_CC = 0x0014 , RT_NVME_REG_CSTS = 0x001c , RT_NVME_REG_NSSR = 0x0020 , RT_NVME_REG_AQA = 0x0024 ,   RT_NVME_REG_ASQ = 0x0028 , RT_NVME_REG_ACQ = 0x0030 , RT_NVME_REG_CMBLOC = 0x0038 , RT_NVME_REG_CMBSZ = 0x003c ,   RT_NVME_REG_BPINFO = 0x0040 , RT_NVME_REG_BPRSEL = 0x0044 , RT_NVME_REG_BPMBL = 0x0048 , RT_NVME_REG_CMBMSC = 0x0050 ,   RT_NVME_REG_CRTO = 0x0068 , RT_NVME_REG_PMRCAP = 0x0e00 , RT_NVME_REG_PMRCTL = 0x0e04 , RT_NVME_REG_PMRSTS = 0x0e08 ,   RT_NVME_REG_PMREBS = 0x0e0c , RT_NVME_REG_PMRSWTP = 0x0e10 , RT_NVME_REG_DBS = 0x1000 }
enum	{   RT_NVME_CC_ENABLE = 1 << 0 , RT_NVME_CC_CSS_NVM = 0 << 4 , RT_NVME_CC_MPS_SHIFT = 7 , RT_NVME_CC_ARB_RR = 0 << 11 ,   RT_NVME_CC_ARB_WRRU = 1 << 11 , RT_NVME_CC_ARB_VS = 7 << 11 , RT_NVME_CC_SHN_NONE = 0 << 14 , RT_NVME_CC_SHN_NORMAL = 1 << 14 ,   RT_NVME_CC_SHN_ABRUPT = 2 << 14 , RT_NVME_CC_SHN_MASK = 3 << 14 , RT_NVME_CC_IOSQES = 6 << 16 , RT_NVME_CC_IOCQES = 4 << 20 ,   RT_NVME_CSTS_RDY = 1 << 0 , RT_NVME_CSTS_CFS = 1 << 1 , RT_NVME_CSTS_SHST_NORMAL = 0 << 2 , RT_NVME_CSTS_SHST_OCCUR = 1 << 2 ,   RT_NVME_CSTS_SHST_CMPLT = 2 << 2 , RT_NVME_CSTS_SHST_MASK = 3 << 2 }
enum	{   RT_NVME_CTRL_CMIC_MULTI_PORT = 1 << 0 , RT_NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1 , RT_NVME_CTRL_CMIC_ANA = 1 << 3 , RT_NVME_CTRL_ONCS_COMPARE = 1 << 0 ,   RT_NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1 , RT_NVME_CTRL_ONCS_DSM = 1 << 2 , RT_NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3 , RT_NVME_CTRL_ONCS_RESERVATIONS = 1 << 5 ,   RT_NVME_CTRL_ONCS_TIMESTAMP = 1 << 6 , RT_NVME_CTRL_VWC_PRESENT = 1 << 0 , RT_NVME_CTRL_OACS_SEC_SUPP = 1 << 0 , RT_NVME_CTRL_OACS_NS_MNGT_SUPP = 1 << 3 ,   RT_NVME_CTRL_OACS_DIRECTIVES = 1 << 5 , RT_NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8 , RT_NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1 , RT_NVME_CTRL_CTRATT_128_ID = 1 << 0 ,   RT_NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1 , RT_NVME_CTRL_CTRATT_NVM_SETS = 1 << 2 , RT_NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3 , RT_NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4 ,   RT_NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5 , RT_NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7 , RT_NVME_CTRL_CTRATT_UUID_LIST = 1 << 9 }
enum	{   RT_NVME_NS_FEAT_THIN = 1 << 0 , RT_NVME_NS_FLBAS_LBA_MASK = 0xf , RT_NVME_NS_FLBAS_LBA_UMASK = 0x60 , RT_NVME_NS_FLBAS_LBA_SHIFT = 1 ,   RT_NVME_NS_FLBAS_META_EXT = 0x10 , RT_NVME_LBAF_RP_BEST = 0 , RT_NVME_LBAF_RP_BETTER = 1 , RT_NVME_LBAF_RP_GOOD = 2 ,   RT_NVME_LBAF_RP_DEGRADED = 3 , RT_NVME_NS_DPC_PI_LAST = 1 << 4 , RT_NVME_NS_DPC_PI_FIRST = 1 << 3 , RT_NVME_NS_DPC_PI_TYPE3 = 1 << 2 ,   RT_NVME_NS_DPC_PI_TYPE2 = 1 << 1 , RT_NVME_NS_DPC_PI_TYPE1 = 1 << 0 , RT_NVME_NS_DPS_PI_FIRST = 1 << 3 , RT_NVME_NS_DPS_PI_MASK = 0x7 ,   RT_NVME_NS_DPS_PI_TYPE1 = 1 , RT_NVME_NS_DPS_PI_TYPE2 = 2 , RT_NVME_NS_DPS_PI_TYPE3 = 3 }

函数
	rt_packed (struct rt_nvme_sgl_desc { rt_le64_t adddress;rt_le32_t length;rt_uint8_t reserved[3];#define SGL_DESC_TYPE_DATA_BLOCK #define SGL_DESC_TYPE_BIT_BUCKET #define SGL_DESC_TYPE_SEGMENT #define SGL_DESC_TYPE_LAST_SEGMENT #define SGL_DESC_TYPE_KEYED_DATA_BLOCK #define SGL_DESC_TYPE_VENDOR_SPECIFIC rt_uint8_t sgl_identify;})
	rt_packed (struct rt_nvme_id_power_state { rt_le16_t mp;NVME_RSVD(1, 1);rt_uint8_t mxps_nops;rt_le32_t enlat;rt_le32_t exlat;rt_uint8_t rrt;rt_uint8_t rrl;rt_uint8_t rwt;rt_uint8_t rwl;rt_le16_t idlp;rt_uint8_t ips;NVME_RSVD(19, 1);rt_le16_t actp;rt_uint8_t apw_aps;NVME_RSVD(23, 9);})
	rt_packed (struct rt_nvme_id_ctrl { rt_le16_t vid;rt_le16_t ssvid;char sn[20];char mn[40];char fr[8];rt_uint8_t rab;rt_uint8_t ieee[3];rt_uint8_t mic;rt_uint8_t mdts;rt_uint16_t cntlid;rt_uint32_t ver;rt_uint32_t rtd3r;rt_uint32_t rtd3e;rt_uint32_t oaes;#define RT_NVME_ID_CTRATT_ELBAS #define RT_NVME_ID_CTRATT_DNVMS #define RT_NVME_ID_CTRATT_DEG #define RT_NVME_ID_CTRATT_VCM #define RT_NVME_ID_CTRATT_FCM #define RT_NVME_ID_CTRATT_MDS #define RT_NVME_ID_CTRATT_UUIDL #define RT_NVME_ID_CTRATT_SQA #define RT_NVME_ID_CTRATT_NG #define RT_NVME_ID_CTRATT_TBKAS #define RT_NVME_ID_CTRATT_PLM #define RT_NVME_ID_CTRATT_EG #define RT_NVME_ID_CTRATT_RRL #define RT_NVME_ID_CTRATT_NVMS #define RT_NVME_ID_CTRATT_NOPSPM #define RT_NVME_ID_CTRATT_HIS rt_uint32_t ctratt;rt_uint16_t rrls;NVME_RSVD(102, 9);rt_uint8_t cntrltype;rt_uint8_t fguid[16];rt_uint16_t crdt1;rt_uint16_t crdt2;rt_uint16_t crdt3;NVME_RSVD(134, 119);#define RT_NVME_ID_NVMSR_NVMEE #define RT_NVME_ID_NVMSR_NVMESD rt_uint8_t nvmsr;#define RT_NVME_ID_VWCI_VWCRV #define RT_NVME_ID_VWCI_VWCR rt_uint8_t vwci;#define RT_NVME_ID_MEC_PCIEME #define RT_NVME_ID_MEC_SMBUSME rt_uint8_t mec;rt_le16_t oacs;rt_uint8_t acl;rt_uint8_t aerl;#define RT_NVME_ID_FRMW_SMUD #define RT_NVME_ID_FRMW_FAWR #define RT_NVME_ID_FRMW_NOFS #define RT_NVME_ID_FRMW_FFSRO rt_uint8_t frmw;rt_uint8_t lpa;rt_uint8_t elpe;rt_uint8_t npss;rt_uint8_t avscc;rt_uint8_t apsta;rt_le16_t wctemp;rt_le16_t cctemp;rt_uint16_t mtfa;rt_uint32_t hmpre;rt_uint32_t hmmin;rt_uint8_t tnvmcap[16];rt_uint8_t unvmcap[16];#define RT_NVME_ID_RPMBS_ASZ #define RT_NVME_ID_RPMBS_TSZ #define RT_NVME_ID_RPMBS_AM #define RT_NVME_ID_RPMBS_NORPMBU rt_uint32_t rpmbs;rt_uint16_t edstt;rt_uint8_t dsto;rt_uint8_t fwug;rt_uint16_t kas;rt_uint16_t hctma;rt_uint16_t mntmt;rt_uint16_t mxtmt;#define RT_NVME_ID_SANICAP_NODMMAS #define RT_NVME_ID_SANICAP_NDI #define RT_NVME_ID_SANICAP_OWS #define RT_NVME_ID_SANICAP_BES #define RT_NVME_ID_SANICAP_CES rt_uint32_t sanicap;rt_uint32_t hmminds;rt_uint16_t hmmaxd;rt_uint16_t nsetidmax;rt_uint16_t endgidmax;rt_uint8_t anatt;rt_uint8_t anacap;rt_uint32_t anagrpmax;rt_uint32_t nanagrpid;rt_uint32_t pels;rt_uint16_t dmid;NVME_RSVD(358, 10);rt_uint8_t megcap[16];NVME_RSVD(384, 128);rt_uint8_t sqes;rt_uint8_t cqes;rt_le16_t maxcmd;rt_le32_t nn;rt_le16_t oncs;rt_le16_t fuses;rt_uint8_t fna;rt_uint8_t vwc;rt_le16_t awun;rt_le16_t awupf;rt_uint8_t nvscc;rt_uint8_t nwpc;rt_le16_t acwu;rt_le16_t cdfs;#define RT_NVME_ID_SGL_SUPPORT_MASK rt_le32_t sgls;rt_uint32_t mnan;char maxdna[16];rt_le32_t maxcna;NVME_RSVD(564, 204);rt_uint8_t subnqn[256];NVME_RSVD(1024, 768);rt_le32_t ioccsz;rt_le32_t iorcsz;rt_le16_t icdoff;rt_uint8_t ctrattr;rt_uint8_t msdbd;rt_le16_t ofcs;rt_uint8_t dctype;NVME_RSVD(1807, 241);struct rt_nvme_id_power_state psd[32];rt_uint8_t vs[1024];})
	rt_packed (struct rt_nvme_id_ns { rt_le64_t nsze;rt_le64_t ncap;rt_le64_t nuse;rt_uint8_t nsfeat;rt_uint8_t nlbaf;rt_uint8_t flbas;rt_uint8_t mc;rt_uint8_t dpc;rt_uint8_t dps;rt_uint8_t nmic;rt_uint8_t rescap;rt_uint8_t fpi;rt_uint8_t dlfeat;rt_le16_t nawun;rt_le16_t nawupf;rt_le16_t nacwu;rt_le16_t nabsn;rt_le16_t nabo;rt_le16_t nabspf;rt_uint16_t noiob;rt_le64_t nvmcap[2];rt_uint16_t npwg;rt_uint16_t npwa;rt_uint16_t npdg;rt_uint16_t npda;rt_uint16_t nows;NVME_RSVD(118, 18);rt_uint32_t anagrpid;NVME_RSVD(139, 3);rt_uint8_t nsattr;rt_uint16_t nvmsetid;rt_uint16_t endgid;rt_uint8_t nguid[16];rt_uint8_t eui64[8];struct rt_nvme_lba_format lbaf[16];NVME_RSVD(171, 192);rt_uint8_t vs[3712];})
rt_err_t	rt_nvme_controller_register (struct rt_nvme_controller *nvme)
rt_err_t	rt_nvme_controller_unregister (struct rt_nvme_controller *nvme)

宏定义说明

NVME_RSVD

#define NVME_RSVD	(		offset,
			bytes_size )

值:

rt_uint8_t __rsvd##offset[bytes_size]

在文件 nvme.h 第 18 行定义.

SGL_DESC_TYPE_DATA_BLOCK

#define SGL_DESC_TYPE_DATA_BLOCK   0x0

SGL_DESC_TYPE_BIT_BUCKET

#define SGL_DESC_TYPE_BIT_BUCKET   0x1

SGL_DESC_TYPE_SEGMENT

#define SGL_DESC_TYPE_SEGMENT   0x2

SGL_DESC_TYPE_LAST_SEGMENT

#define SGL_DESC_TYPE_LAST_SEGMENT   0x3

SGL_DESC_TYPE_KEYED_DATA_BLOCK

#define SGL_DESC_TYPE_KEYED_DATA_BLOCK   0x4

SGL_DESC_TYPE_VENDOR_SPECIFIC

#define SGL_DESC_TYPE_VENDOR_SPECIFIC   0xf

RT_NVME_CAP_MQES

#define RT_NVME_CAP_MQES

(

cap

)

值:

((cap) & 0xffff)

在文件 nvme.h 第 494 行定义.

RT_NVME_CAP_TIMEOUT

#define RT_NVME_CAP_TIMEOUT

(

cap

)

值:

(((cap) >> 24) & 0xff)

在文件 nvme.h 第 495 行定义.

RT_NVME_CAP_STRIDE

#define RT_NVME_CAP_STRIDE

(

cap

)

值:

(((cap) >> 32) & 0xf)

在文件 nvme.h 第 496 行定义.

RT_NVME_CAP_MPSMIN

#define RT_NVME_CAP_MPSMIN

(

cap

)

值:

(((cap) >> 48) & 0xf)

在文件 nvme.h 第 497 行定义.

RT_NVME_CAP_MPSMAX

#define RT_NVME_CAP_MPSMAX

(

cap

)

值:

(((cap) >> 52) & 0xf)

在文件 nvme.h 第 498 行定义.

RT_NVME_VS

#define RT_NVME_VS	(		major,
			minor )

值:

(((major) << 16) | ((minor) << 8))

在文件 nvme.h 第 500 行定义.

RT_NVME_AQ_DEPTH

#define RT_NVME_AQ_DEPTH   32

在文件 nvme.h 第 502 行定义.

RT_NVME_NR_AEN_COMMANDS

#define RT_NVME_NR_AEN_COMMANDS   1

在文件 nvme.h 第 503 行定义.

RT_NVME_AQ_BLK_MQ_DEPTH

#define RT_NVME_AQ_BLK_MQ_DEPTH   (RT_NVME_AQ_DEPTH - RT_NVME_NR_AEN_COMMANDS)

在文件 nvme.h 第 504 行定义.

RT_NVME_AQ_MQ_TAG_DEPTH

#define RT_NVME_AQ_MQ_TAG_DEPTH   (RT_NVME_AQ_BLK_MQ_DEPTH - 1)

在文件 nvme.h 第 505 行定义.

RT_NVME_ID_CTRATT_ELBAS

#define RT_NVME_ID_CTRATT_ELBAS   15 /* Extended LBA Formats Supported */

RT_NVME_ID_CTRATT_DNVMS

#define RT_NVME_ID_CTRATT_DNVMS   14 /* Delete NVM Set */

RT_NVME_ID_CTRATT_DEG

#define RT_NVME_ID_CTRATT_DEG   13 /* Delete Endurance Group */

RT_NVME_ID_CTRATT_VCM

#define RT_NVME_ID_CTRATT_VCM   12 /* Variable Capacity Management */

RT_NVME_ID_CTRATT_FCM

#define RT_NVME_ID_CTRATT_FCM   11 /* Fixed Capacity Management */

RT_NVME_ID_CTRATT_MDS

#define RT_NVME_ID_CTRATT_MDS   10 /* Multi-Domain Subsystem */

RT_NVME_ID_CTRATT_UUIDL

#define RT_NVME_ID_CTRATT_UUIDL   9 /* UUID List */

RT_NVME_ID_CTRATT_SQA

#define RT_NVME_ID_CTRATT_SQA   8 /* SQ Associations */

RT_NVME_ID_CTRATT_NG

#define RT_NVME_ID_CTRATT_NG   7 /* Namespace Granularity */

RT_NVME_ID_CTRATT_TBKAS

#define RT_NVME_ID_CTRATT_TBKAS   6 /* Traffic Based Keep Alive Support */

RT_NVME_ID_CTRATT_PLM

#define RT_NVME_ID_CTRATT_PLM   5 /* Predictable Latency Mode */

RT_NVME_ID_CTRATT_EG

#define RT_NVME_ID_CTRATT_EG   4 /* Endurance Groups */

RT_NVME_ID_CTRATT_RRL

#define RT_NVME_ID_CTRATT_RRL   3 /* Read Recovery Levels */

RT_NVME_ID_CTRATT_NVMS

#define RT_NVME_ID_CTRATT_NVMS   2 /* NVM Sets */

RT_NVME_ID_CTRATT_NOPSPM

#define RT_NVME_ID_CTRATT_NOPSPM   1 /* Non-Operational Power State Permissive Mode */

RT_NVME_ID_CTRATT_HIS

#define RT_NVME_ID_CTRATT_HIS   0 /* Host Identifier Support */

RT_NVME_ID_NVMSR_NVMEE

#define RT_NVME_ID_NVMSR_NVMEE   1 /* NVMe Enclosure */

RT_NVME_ID_NVMSR_NVMESD

#define RT_NVME_ID_NVMSR_NVMESD   0 /* NVMe Storage Device */

RT_NVME_ID_VWCI_VWCRV

#define RT_NVME_ID_VWCI_VWCRV   7 /* VPD Write Cycles Remaining Valid */

RT_NVME_ID_VWCI_VWCR

#define RT_NVME_ID_VWCI_VWCR   0 /* VPD Write Cycles Remaining */

RT_NVME_ID_MEC_PCIEME

#define RT_NVME_ID_MEC_PCIEME   1 /* PCIe Port Management Endpoint */

RT_NVME_ID_MEC_SMBUSME

#define RT_NVME_ID_MEC_SMBUSME   0 /* SMBus/I2C Port Management Endpoint */

RT_NVME_ID_FRMW_SMUD

#define RT_NVME_ID_FRMW_SMUD   5 /* Support Multiple Update Detection */

RT_NVME_ID_FRMW_FAWR

#define RT_NVME_ID_FRMW_FAWR   4 /* Firmware Activation Without Reset */

RT_NVME_ID_FRMW_NOFS

#define RT_NVME_ID_FRMW_NOFS   1 /* Number Of Firmware Slots */

RT_NVME_ID_FRMW_FFSRO

#define RT_NVME_ID_FRMW_FFSRO   0 /* First Firmware Slot Read Only */

RT_NVME_ID_RPMBS_ASZ

#define RT_NVME_ID_RPMBS_ASZ   24 /* Access Size */

RT_NVME_ID_RPMBS_TSZ

#define RT_NVME_ID_RPMBS_TSZ   16 /* Total Size */

RT_NVME_ID_RPMBS_AM

#define RT_NVME_ID_RPMBS_AM   3 /* Authentication Method */

RT_NVME_ID_RPMBS_NORPMBU

#define RT_NVME_ID_RPMBS_NORPMBU   2 /* Number of RPMB Units */

RT_NVME_ID_SANICAP_NODMMAS

#define RT_NVME_ID_SANICAP_NODMMAS   30 /* No-Deallocate Modifies Media After Sanitize */

RT_NVME_ID_SANICAP_NDI

#define RT_NVME_ID_SANICAP_NDI   29 /* No-Deallocate Inhibited */

RT_NVME_ID_SANICAP_OWS

#define RT_NVME_ID_SANICAP_OWS   2 /* Overwrite Support */

RT_NVME_ID_SANICAP_BES

#define RT_NVME_ID_SANICAP_BES   1 /* Block Erase Support */

RT_NVME_ID_SANICAP_CES

#define RT_NVME_ID_SANICAP_CES   0 /* Crypto Erase Support */

RT_NVME_ID_SGL_SUPPORT_MASK

#define RT_NVME_ID_SGL_SUPPORT_MASK   0x3

RT_USING_NVME_QUEUE

#define RT_USING_NVME_QUEUE   (1 + (RT_USING_NVME_IO_QUEUE * RT_CPUS_NR))

在文件 nvme.h 第 850 行定义.

rt_disk_to_nvme_device

#define rt_disk_to_nvme_device

(

disk

)

值:

rt_container_of(disk, struct rt_nvme_device, parent)

在文件 nvme.h 第 880 行定义.

枚举类型说明

anonymous enum

anonymous enum

枚举值
RT_NVME_SC_SUCCESS	0x0
RT_NVME_SC_INVALID_OPCODE	0x1
RT_NVME_SC_INVALID_FIELD	0x2
RT_NVME_SC_CMDID_CONFLICT	0x3
RT_NVME_SC_DATA_XFER_ERROR	0x4
RT_NVME_SC_POWER_LOSS	0x5
RT_NVME_SC_INTERNAL	0x6
RT_NVME_SC_ABORT_REQ	0x7
RT_NVME_SC_ABORT_QUEUE	0x8
RT_NVME_SC_FUSED_FAIL	0x9
RT_NVME_SC_FUSED_MISSING	0xa
RT_NVME_SC_INVALID_NS	0xb
RT_NVME_SC_CMD_SEQ_ERROR	0xc
RT_NVME_SC_SGL_INVALID_LAST	0xd
RT_NVME_SC_SGL_INVALID_COUNT	0xe
RT_NVME_SC_SGL_INVALID_DATA	0xf
RT_NVME_SC_SGL_INVALID_METADATA	0x10
RT_NVME_SC_SGL_INVALID_TYPE	0x11
RT_NVME_SC_CMB_INVALID_USE	0x12
RT_NVME_SC_PRP_INVALID_OFFSET	0x13
RT_NVME_SC_ATOMIC_WU_EXCEEDED	0x14
RT_NVME_SC_OP_DENIED	0x15
RT_NVME_SC_SGL_INVALID_OFFSET	0x16
RT_NVME_SC_RESERVED	0x17
RT_NVME_SC_HOST_ID_INCONSIST	0x18
RT_NVME_SC_KA_TIMEOUT_EXPIRED	0x19
RT_NVME_SC_KA_TIMEOUT_INVALID	0x1a
RT_NVME_SC_ABORTED_PREEMPT_ABORT	0x1b
RT_NVME_SC_SANITIZE_FAILED	0x1c
RT_NVME_SC_SANITIZE_IN_PROGRESS	0x1d
RT_NVME_SC_SGL_INVALID_GRANULARITY	0x1e
RT_NVME_SC_CMD_NOT_SUP_CMB_QUEUE	0x1f
RT_NVME_SC_NS_WRITE_PROTECTED	0x20
RT_NVME_SC_CMD_INTERRUPTED	0x21
RT_NVME_SC_TRANSIENT_TR_ERR	0x22
RT_NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY	0x24
RT_NVME_SC_INVALID_IO_CMD_SET	0x2c
RT_NVME_SC_LBA_RANGE	0x80
RT_NVME_SC_CAP_EXCEEDED	0x81
RT_NVME_SC_NS_NOT_READY	0x82
RT_NVME_SC_RESERVATION_CONFLICT	0x83
RT_NVME_SC_FORMAT_IN_PROGRESS	0x84
RT_NVME_SC_CQ_INVALID	0x100
RT_NVME_SC_QID_INVALID	0x101
RT_NVME_SC_QUEUE_SIZE	0x102
RT_NVME_SC_ABORT_LIMIT	0x103
RT_NVME_SC_ABORT_MISSING	0x104
RT_NVME_SC_ASYNC_LIMIT	0x105
RT_NVME_SC_FIRMWARE_SLOT	0x106
RT_NVME_SC_FIRMWARE_IMAGE	0x107
RT_NVME_SC_INVALID_VECTOR	0x108
RT_NVME_SC_INVALID_LOG_PAGE	0x109
RT_NVME_SC_INVALID_FORMAT	0x10a
RT_NVME_SC_FW_NEEDS_CONV_RESET	0x10b
RT_NVME_SC_INVALID_QUEUE	0x10c
RT_NVME_SC_FEATURE_NOT_SAVEABLE	0x10d
RT_NVME_SC_FEATURE_NOT_CHANGEABLE	0x10e
RT_NVME_SC_FEATURE_NOT_PER_NS	0x10f
RT_NVME_SC_FW_NEEDS_SUBSYS_RESET	0x110
RT_NVME_SC_FW_NEEDS_RESET	0x111
RT_NVME_SC_FW_NEEDS_MAX_TIME	0x112
RT_NVME_SC_FW_ACTIVATE_PROHIBITED	0x113
RT_NVME_SC_OVERLAPPING_RANGE	0x114
RT_NVME_SC_NS_INSUFFICIENT_CAP	0x115
RT_NVME_SC_NS_ID_UNAVAILABLE	0x116
RT_NVME_SC_NS_ALREADY_ATTACHED	0x118
RT_NVME_SC_NS_IS_PRIVATE	0x119
RT_NVME_SC_NS_NOT_ATTACHED	0x11a
RT_NVME_SC_THIN_PROV_NOT_SUPP	0x11b
RT_NVME_SC_CTRL_LIST_INVALID	0x11c
RT_NVME_SC_SELT_TEST_IN_PROGRESS	0x11d
RT_NVME_SC_BP_WRITE_PROHIBITED	0x11e
RT_NVME_SC_CTRL_ID_INVALID	0x11f
RT_NVME_SC_SEC_CTRL_STATE_INVALID	0x120
RT_NVME_SC_CTRL_RES_NUM_INVALID	0x121
RT_NVME_SC_RES_ID_INVALID	0x122
RT_NVME_SC_PMR_SAN_PROHIBITED	0x123
RT_NVME_SC_ANA_GROUP_ID_INVALID	0x124
RT_NVME_SC_ANA_ATTACH_FAILED	0x125
RT_NVME_SC_BAD_ATTRIBUTES	0x180
RT_NVME_SC_INVALID_PI	0x181
RT_NVME_SC_READ_ONLY	0x182
RT_NVME_SC_ONCS_NOT_SUPPORTED	0x183
RT_NVME_SC_CONNECT_FORMAT	0x180
RT_NVME_SC_CONNECT_CTRL_BUSY	0x181
RT_NVME_SC_CONNECT_INVALID_PARAM	0x182
RT_NVME_SC_CONNECT_RESTART_DISC	0x183
RT_NVME_SC_CONNECT_INVALID_HOST	0x184
RT_NVME_SC_DISCOVERY_RESTART	0x190
RT_NVME_SC_AUTH_REQUIRED	0x191
RT_NVME_SC_ZONE_BOUNDARY_ERROR	0x1b8
RT_NVME_SC_ZONE_FULL	0x1b9
RT_NVME_SC_ZONE_READ_ONLY	0x1ba
RT_NVME_SC_ZONE_OFFLINE	0x1bb
RT_NVME_SC_ZONE_INVALID_WRITE	0x1bc
RT_NVME_SC_ZONE_TOO_MANY_ACTIVE	0x1bd
RT_NVME_SC_ZONE_TOO_MANY_OPEN	0x1be
RT_NVME_SC_ZONE_INVALID_TRANSITION	0x1bf
RT_NVME_SC_WRITE_FAULT	0x280
RT_NVME_SC_READ_ERROR	0x281
RT_NVME_SC_GUARD_CHECK	0x282
RT_NVME_SC_APPTAG_CHECK	0x283
RT_NVME_SC_REFTAG_CHECK	0x284
RT_NVME_SC_COMPARE_FAILED	0x285
RT_NVME_SC_ACCESS_DENIED	0x286
RT_NVME_SC_UNWRITTEN_BLOCK	0x287
RT_NVME_SC_INTERNAL_PATH_ERROR	0x300
RT_NVME_SC_ANA_PERSISTENT_LOSS	0x301
RT_NVME_SC_ANA_INACCESSIBLE	0x302
RT_NVME_SC_ANA_TRANSITION	0x303
RT_NVME_SC_CTRL_PATH_ERROR	0x360
RT_NVME_SC_HOST_PATH_ERROR	0x370
RT_NVME_SC_HOST_ABORTED_CMD	0x371
RT_NVME_SC_CRD	0x1800
RT_NVME_SC_MORE	0x2000
RT_NVME_SC_DNR	0x4000

在文件 nvme.h 第 20 行定义.

{
    /*
     * Generic Command Status:
     */
    RT_NVME_SC_SUCCESS                          = 0x0,
    RT_NVME_SC_INVALID_OPCODE                   = 0x1,
    RT_NVME_SC_INVALID_FIELD                    = 0x2,
    RT_NVME_SC_CMDID_CONFLICT                   = 0x3,
    RT_NVME_SC_DATA_XFER_ERROR                  = 0x4,
    RT_NVME_SC_POWER_LOSS                       = 0x5,
    RT_NVME_SC_INTERNAL                         = 0x6,
    RT_NVME_SC_ABORT_REQ                        = 0x7,
    RT_NVME_SC_ABORT_QUEUE                      = 0x8,
    RT_NVME_SC_FUSED_FAIL                       = 0x9,
    RT_NVME_SC_FUSED_MISSING                    = 0xa,
    RT_NVME_SC_INVALID_NS                       = 0xb,
    RT_NVME_SC_CMD_SEQ_ERROR                    = 0xc,
    RT_NVME_SC_SGL_INVALID_LAST                 = 0xd,
    RT_NVME_SC_SGL_INVALID_COUNT                = 0xe,
    RT_NVME_SC_SGL_INVALID_DATA                 = 0xf,
    RT_NVME_SC_SGL_INVALID_METADATA             = 0x10,
    RT_NVME_SC_SGL_INVALID_TYPE                 = 0x11,
    RT_NVME_SC_CMB_INVALID_USE                  = 0x12,
    RT_NVME_SC_PRP_INVALID_OFFSET               = 0x13,
    RT_NVME_SC_ATOMIC_WU_EXCEEDED               = 0x14,
    RT_NVME_SC_OP_DENIED                        = 0x15,
    RT_NVME_SC_SGL_INVALID_OFFSET               = 0x16,
    RT_NVME_SC_RESERVED                         = 0x17,
    RT_NVME_SC_HOST_ID_INCONSIST                = 0x18,
    RT_NVME_SC_KA_TIMEOUT_EXPIRED               = 0x19,
    RT_NVME_SC_KA_TIMEOUT_INVALID               = 0x1a,
    RT_NVME_SC_ABORTED_PREEMPT_ABORT            = 0x1b,
    RT_NVME_SC_SANITIZE_FAILED                  = 0x1c,
    RT_NVME_SC_SANITIZE_IN_PROGRESS             = 0x1d,
    RT_NVME_SC_SGL_INVALID_GRANULARITY          = 0x1e,
    RT_NVME_SC_CMD_NOT_SUP_CMB_QUEUE            = 0x1f,
    RT_NVME_SC_NS_WRITE_PROTECTED               = 0x20,
    RT_NVME_SC_CMD_INTERRUPTED                  = 0x21,
    RT_NVME_SC_TRANSIENT_TR_ERR                 = 0x22,
    RT_NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY    = 0x24,
    RT_NVME_SC_INVALID_IO_CMD_SET               = 0x2c,
 
    RT_NVME_SC_LBA_RANGE                        = 0x80,
    RT_NVME_SC_CAP_EXCEEDED                     = 0x81,
    RT_NVME_SC_NS_NOT_READY                     = 0x82,
    RT_NVME_SC_RESERVATION_CONFLICT             = 0x83,
    RT_NVME_SC_FORMAT_IN_PROGRESS               = 0x84,
 
    /*
     * Command Specific Status:
     */
    RT_NVME_SC_CQ_INVALID                       = 0x100,
    RT_NVME_SC_QID_INVALID                      = 0x101,
    RT_NVME_SC_QUEUE_SIZE                       = 0x102,
    RT_NVME_SC_ABORT_LIMIT                      = 0x103,
    RT_NVME_SC_ABORT_MISSING                    = 0x104,
    RT_NVME_SC_ASYNC_LIMIT                      = 0x105,
    RT_NVME_SC_FIRMWARE_SLOT                    = 0x106,
    RT_NVME_SC_FIRMWARE_IMAGE                   = 0x107,
    RT_NVME_SC_INVALID_VECTOR                   = 0x108,
    RT_NVME_SC_INVALID_LOG_PAGE                 = 0x109,
    RT_NVME_SC_INVALID_FORMAT                   = 0x10a,
    RT_NVME_SC_FW_NEEDS_CONV_RESET              = 0x10b,
    RT_NVME_SC_INVALID_QUEUE                    = 0x10c,
    RT_NVME_SC_FEATURE_NOT_SAVEABLE             = 0x10d,
    RT_NVME_SC_FEATURE_NOT_CHANGEABLE           = 0x10e,
    RT_NVME_SC_FEATURE_NOT_PER_NS               = 0x10f,
    RT_NVME_SC_FW_NEEDS_SUBSYS_RESET            = 0x110,
    RT_NVME_SC_FW_NEEDS_RESET                   = 0x111,
    RT_NVME_SC_FW_NEEDS_MAX_TIME                = 0x112,
    RT_NVME_SC_FW_ACTIVATE_PROHIBITED           = 0x113,
    RT_NVME_SC_OVERLAPPING_RANGE                = 0x114,
    RT_NVME_SC_NS_INSUFFICIENT_CAP              = 0x115,
    RT_NVME_SC_NS_ID_UNAVAILABLE                = 0x116,
    RT_NVME_SC_NS_ALREADY_ATTACHED              = 0x118,
    RT_NVME_SC_NS_IS_PRIVATE                    = 0x119,
    RT_NVME_SC_NS_NOT_ATTACHED                  = 0x11a,
    RT_NVME_SC_THIN_PROV_NOT_SUPP               = 0x11b,
    RT_NVME_SC_CTRL_LIST_INVALID                = 0x11c,
    RT_NVME_SC_SELT_TEST_IN_PROGRESS            = 0x11d,
    RT_NVME_SC_BP_WRITE_PROHIBITED              = 0x11e,
    RT_NVME_SC_CTRL_ID_INVALID                  = 0x11f,
    RT_NVME_SC_SEC_CTRL_STATE_INVALID           = 0x120,
    RT_NVME_SC_CTRL_RES_NUM_INVALID             = 0x121,
    RT_NVME_SC_RES_ID_INVALID                   = 0x122,
    RT_NVME_SC_PMR_SAN_PROHIBITED               = 0x123,
    RT_NVME_SC_ANA_GROUP_ID_INVALID             = 0x124,
    RT_NVME_SC_ANA_ATTACH_FAILED                = 0x125,
 
    /*
     * I/O Command Set Specific - NVM commands:
     */
    RT_NVME_SC_BAD_ATTRIBUTES                   = 0x180,
    RT_NVME_SC_INVALID_PI                       = 0x181,
    RT_NVME_SC_READ_ONLY                        = 0x182,
    RT_NVME_SC_ONCS_NOT_SUPPORTED               = 0x183,
 
    /*
     * I/O Command Set Specific - Fabrics commands:
     */
    RT_NVME_SC_CONNECT_FORMAT                   = 0x180,
    RT_NVME_SC_CONNECT_CTRL_BUSY                = 0x181,
    RT_NVME_SC_CONNECT_INVALID_PARAM            = 0x182,
    RT_NVME_SC_CONNECT_RESTART_DISC             = 0x183,
    RT_NVME_SC_CONNECT_INVALID_HOST             = 0x184,
 
    RT_NVME_SC_DISCOVERY_RESTART                = 0x190,
    RT_NVME_SC_AUTH_REQUIRED                    = 0x191,
 
    /*
     * I/O Command Set Specific - Zoned commands:
     */
    RT_NVME_SC_ZONE_BOUNDARY_ERROR              = 0x1b8,
    RT_NVME_SC_ZONE_FULL                        = 0x1b9,
    RT_NVME_SC_ZONE_READ_ONLY                   = 0x1ba,
    RT_NVME_SC_ZONE_OFFLINE                     = 0x1bb,
    RT_NVME_SC_ZONE_INVALID_WRITE               = 0x1bc,
    RT_NVME_SC_ZONE_TOO_MANY_ACTIVE             = 0x1bd,
    RT_NVME_SC_ZONE_TOO_MANY_OPEN               = 0x1be,
    RT_NVME_SC_ZONE_INVALID_TRANSITION          = 0x1bf,
 
    /*
     * Media and Data Integrity Errors:
     */
    RT_NVME_SC_WRITE_FAULT                      = 0x280,
    RT_NVME_SC_READ_ERROR                       = 0x281,
    RT_NVME_SC_GUARD_CHECK                      = 0x282,
    RT_NVME_SC_APPTAG_CHECK                     = 0x283,
    RT_NVME_SC_REFTAG_CHECK                     = 0x284,
    RT_NVME_SC_COMPARE_FAILED                   = 0x285,
    RT_NVME_SC_ACCESS_DENIED                    = 0x286,
    RT_NVME_SC_UNWRITTEN_BLOCK                  = 0x287,
 
    /*
     * Path-related Errors:
     */
    RT_NVME_SC_INTERNAL_PATH_ERROR              = 0x300,
    RT_NVME_SC_ANA_PERSISTENT_LOSS              = 0x301,
    RT_NVME_SC_ANA_INACCESSIBLE                 = 0x302,
    RT_NVME_SC_ANA_TRANSITION                   = 0x303,
    RT_NVME_SC_CTRL_PATH_ERROR                  = 0x360,
    RT_NVME_SC_HOST_PATH_ERROR                  = 0x370,
    RT_NVME_SC_HOST_ABORTED_CMD                 = 0x371,
 
    RT_NVME_SC_CRD                              = 0x1800,
    RT_NVME_SC_MORE                             = 0x2000,
    RT_NVME_SC_DNR                              = 0x4000,
};

anonymous enum

anonymous enum

枚举值
RT_NVME_ADMIN_OPCODE_DELETE_SQ	0x00
RT_NVME_ADMIN_OPCODE_CREATE_SQ	0x01
RT_NVME_ADMIN_OPCODE_GET_LOG_PAGE	0x02
RT_NVME_ADMIN_OPCODE_DELETE_CQ	0x04
RT_NVME_ADMIN_OPCODE_CREATE_CQ	0x05
RT_NVME_ADMIN_OPCODE_IDENTIFY	0x06
RT_NVME_ADMIN_OPCODE_ABORT_CMD	0x08
RT_NVME_ADMIN_OPCODE_SET_FEATURES	0x09
RT_NVME_ADMIN_OPCODE_GET_FEATURES	0x0a
RT_NVME_ADMIN_OPCODE_ASYNC_EVENT	0x0c
RT_NVME_ADMIN_OPCODE_NS_MGMT	0x0d
RT_NVME_ADMIN_OPCODE_ACTIVATE_FW	0x10
RT_NVME_ADMIN_OPCODE_DOWNLOAD_FW	0x11
RT_NVME_ADMIN_OPCODE_DEV_SELF_TEST	0x14
RT_NVME_ADMIN_OPCODE_NS_ATTACH	0x15
RT_NVME_ADMIN_OPCODE_KEEP_ALIVE	0x18
RT_NVME_ADMIN_OPCODE_DIRECTIVE_SEND	0x19
RT_NVME_ADMIN_OPCODE_DIRECTIVE_RECV	0x1a
RT_NVME_ADMIN_OPCODE_VIRTUAL_MGMT	0x1c
RT_NVME_ADMIN_OPCODE_NVME_MI_SEND	0x1d
RT_NVME_ADMIN_OPCODE_NVME_MI_RECV	0x1e
RT_NVME_ADMIN_OPCODE_DBBUF	0x7c
RT_NVME_ADMIN_OPCODE_FORMAT_NVM	0x80
RT_NVME_ADMIN_OPCODE_SECURITY_SEND	0x81
RT_NVME_ADMIN_OPCODE_SECURITY_RECV	0x82
RT_NVME_ADMIN_OPCODE_SANITIZE_NVM	0x84
RT_NVME_ADMIN_OPCODE_GET_LBA_STATUS	0x86
RT_NVME_ADMIN_OPCODE_VENDOR_START	0xc0

在文件 nvme.h 第 171 行定义.

{
    RT_NVME_ADMIN_OPCODE_DELETE_SQ          = 0x00,
    RT_NVME_ADMIN_OPCODE_CREATE_SQ          = 0x01,
    RT_NVME_ADMIN_OPCODE_GET_LOG_PAGE       = 0x02,
    RT_NVME_ADMIN_OPCODE_DELETE_CQ          = 0x04,
    RT_NVME_ADMIN_OPCODE_CREATE_CQ          = 0x05,
    RT_NVME_ADMIN_OPCODE_IDENTIFY           = 0x06,
    RT_NVME_ADMIN_OPCODE_ABORT_CMD          = 0x08,
    RT_NVME_ADMIN_OPCODE_SET_FEATURES       = 0x09,
    RT_NVME_ADMIN_OPCODE_GET_FEATURES       = 0x0a,
    RT_NVME_ADMIN_OPCODE_ASYNC_EVENT        = 0x0c,
    RT_NVME_ADMIN_OPCODE_NS_MGMT            = 0x0d,
    RT_NVME_ADMIN_OPCODE_ACTIVATE_FW        = 0x10,
    RT_NVME_ADMIN_OPCODE_DOWNLOAD_FW        = 0x11,
    RT_NVME_ADMIN_OPCODE_DEV_SELF_TEST      = 0x14,
    RT_NVME_ADMIN_OPCODE_NS_ATTACH          = 0x15,
    RT_NVME_ADMIN_OPCODE_KEEP_ALIVE         = 0x18,
    RT_NVME_ADMIN_OPCODE_DIRECTIVE_SEND     = 0x19,
    RT_NVME_ADMIN_OPCODE_DIRECTIVE_RECV     = 0x1a,
    RT_NVME_ADMIN_OPCODE_VIRTUAL_MGMT       = 0x1c,
    RT_NVME_ADMIN_OPCODE_NVME_MI_SEND       = 0x1d,
    RT_NVME_ADMIN_OPCODE_NVME_MI_RECV       = 0x1e,
    RT_NVME_ADMIN_OPCODE_DBBUF              = 0x7c,
    RT_NVME_ADMIN_OPCODE_FORMAT_NVM         = 0x80,
    RT_NVME_ADMIN_OPCODE_SECURITY_SEND      = 0x81,
    RT_NVME_ADMIN_OPCODE_SECURITY_RECV      = 0x82,
    RT_NVME_ADMIN_OPCODE_SANITIZE_NVM       = 0x84,
    RT_NVME_ADMIN_OPCODE_GET_LBA_STATUS     = 0x86,
    RT_NVME_ADMIN_OPCODE_VENDOR_START       = 0xc0,
};

anonymous enum

anonymous enum

枚举值
RT_NVME_CMD_FLUSH	0x00
RT_NVME_CMD_WRITE	0x01
RT_NVME_CMD_READ	0x02
RT_NVME_CMD_WRITE_UNCOR	0x04
RT_NVME_CMD_COMPARE	0x05
RT_NVME_CMD_WRITE_ZEROES	0x08
RT_NVME_CMD_DSM	0x09
RT_NVME_CMD_VERIFY	0x0c
RT_NVME_CMD_RESV_REGISTER	0x0d
RT_NVME_CMD_RESV_REPORT	0x0e
RT_NVME_CMD_RESV_ACQUIRE	0x11
RT_NVME_CMD_RESV_RELEASE	0x15
RT_NVME_CMD_ZONE_MGMT_SEND	0x79
RT_NVME_CMD_ZONE_MGMT_RECV	0x7a
RT_NVME_CMD_ZONE_APPEND	0x7d
RT_NVME_CMD_VENDOR_START	0x80

在文件 nvme.h 第 204 行定义.

{
    RT_NVME_CMD_FLUSH           = 0x00,
    RT_NVME_CMD_WRITE           = 0x01,
    RT_NVME_CMD_READ            = 0x02,
    RT_NVME_CMD_WRITE_UNCOR     = 0x04,
    RT_NVME_CMD_COMPARE         = 0x05,
    RT_NVME_CMD_WRITE_ZEROES    = 0x08,
    RT_NVME_CMD_DSM             = 0x09,
    RT_NVME_CMD_VERIFY          = 0x0c,
    RT_NVME_CMD_RESV_REGISTER   = 0x0d,
    RT_NVME_CMD_RESV_REPORT     = 0x0e,
    RT_NVME_CMD_RESV_ACQUIRE    = 0x11,
    RT_NVME_CMD_RESV_RELEASE    = 0x15,
    RT_NVME_CMD_ZONE_MGMT_SEND  = 0x79,
    RT_NVME_CMD_ZONE_MGMT_RECV  = 0x7a,
    RT_NVME_CMD_ZONE_APPEND     = 0x7d,
    RT_NVME_CMD_VENDOR_START    = 0x80,
};

anonymous enum

anonymous enum

枚举值
RT_NVME_PSDT_PRP	0x0
RT_NVME_PSDT_SGL_MPTR_CONTIGUOUS	0x1
RT_NVME_PSDT_SGL_MPTR_SGL	0x2

在文件 nvme.h 第 224 行定义.

{
    RT_NVME_PSDT_PRP                    = 0x0,
    RT_NVME_PSDT_SGL_MPTR_CONTIGUOUS    = 0x1,
    RT_NVME_PSDT_SGL_MPTR_SGL           = 0x2,
};

anonymous enum

anonymous enum

枚举值
RT_NVME_CMD_FLAGS_FUSE_SHIFT	0x00
RT_NVME_CMD_FLAGS_PSDT_SHIFT	0x06

在文件 nvme.h 第 232 行定义.

{
    RT_NVME_CMD_FLAGS_FUSE_SHIFT        = 0x00,
    RT_NVME_CMD_FLAGS_PSDT_SHIFT        = 0x06,
};

anonymous enum

anonymous enum

枚举值
RT_NVME_RW_LR	1 << 15
RT_NVME_RW_FUA	1 << 14
RT_NVME_RW_APPEND_PIREMAP	1 << 9
RT_NVME_RW_DSM_FREQ_UNSPEC	0
RT_NVME_RW_DSM_FREQ_TYPICAL	1
RT_NVME_RW_DSM_FREQ_RARE	2
RT_NVME_RW_DSM_FREQ_READS	3
RT_NVME_RW_DSM_FREQ_WRITES	4
RT_NVME_RW_DSM_FREQ_RW	5
RT_NVME_RW_DSM_FREQ_ONCE	6
RT_NVME_RW_DSM_FREQ_PREFETCH	7
RT_NVME_RW_DSM_FREQ_TEMP	8
RT_NVME_RW_DSM_LATENCY_NONE	0 << 4
RT_NVME_RW_DSM_LATENCY_IDLE	1 << 4
RT_NVME_RW_DSM_LATENCY_NORM	2 << 4
RT_NVME_RW_DSM_LATENCY_LOW	3 << 4
RT_NVME_RW_DSM_SEQ_REQ	1 << 6
RT_NVME_RW_DSM_COMPRESSED	1 << 7
RT_NVME_RW_PRINFO_PRCHK_REF	1 << 10
RT_NVME_RW_PRINFO_PRCHK_APP	1 << 11
RT_NVME_RW_PRINFO_PRCHK_GUARD	1 << 12
RT_NVME_RW_PRINFO_PRACT	1 << 13
RT_NVME_RW_DTYPE_STREAMS	1 << 4
RT_NVME_WZ_DEAC	1 << 9

在文件 nvme.h 第 291 行定义.

{
    RT_NVME_RW_LR                   = 1 << 15,
    RT_NVME_RW_FUA                  = 1 << 14,
    RT_NVME_RW_APPEND_PIREMAP       = 1 << 9,
    RT_NVME_RW_DSM_FREQ_UNSPEC      = 0,
    RT_NVME_RW_DSM_FREQ_TYPICAL     = 1,
    RT_NVME_RW_DSM_FREQ_RARE        = 2,
    RT_NVME_RW_DSM_FREQ_READS       = 3,
    RT_NVME_RW_DSM_FREQ_WRITES      = 4,
    RT_NVME_RW_DSM_FREQ_RW          = 5,
    RT_NVME_RW_DSM_FREQ_ONCE        = 6,
    RT_NVME_RW_DSM_FREQ_PREFETCH    = 7,
    RT_NVME_RW_DSM_FREQ_TEMP        = 8,
    RT_NVME_RW_DSM_LATENCY_NONE     = 0 << 4,
    RT_NVME_RW_DSM_LATENCY_IDLE     = 1 << 4,
    RT_NVME_RW_DSM_LATENCY_NORM     = 2 << 4,
    RT_NVME_RW_DSM_LATENCY_LOW      = 3 << 4,
    RT_NVME_RW_DSM_SEQ_REQ          = 1 << 6,
    RT_NVME_RW_DSM_COMPRESSED       = 1 << 7,
    RT_NVME_RW_PRINFO_PRCHK_REF     = 1 << 10,
    RT_NVME_RW_PRINFO_PRCHK_APP     = 1 << 11,
    RT_NVME_RW_PRINFO_PRCHK_GUARD   = 1 << 12,
    RT_NVME_RW_PRINFO_PRACT         = 1 << 13,
    RT_NVME_RW_DTYPE_STREAMS        = 1 << 4,
    RT_NVME_WZ_DEAC                 = 1 << 9,
};

anonymous enum

anonymous enum

枚举值
RT_NVME_QUEUE_PHYS_CONTIG	(1 << 0)
RT_NVME_CQ_IRQ_ENABLED	(1 << 1)
RT_NVME_SQ_PRIO_URGENT	(0 << 1)
RT_NVME_SQ_PRIO_HIGH	(1 << 1)
RT_NVME_SQ_PRIO_MEDIUM	(2 << 1)
RT_NVME_SQ_PRIO_LOW	(3 << 1)
RT_NVME_FEAT_ARBITRATION	0x01
RT_NVME_FEAT_POWER_MGMT	0x02
RT_NVME_FEAT_LBA_RANGE	0x03
RT_NVME_FEAT_TEMP_THRESH	0x04
RT_NVME_FEAT_ERR_RECOVERY	0x05
RT_NVME_FEAT_VOLATILE_WC	0x06
RT_NVME_FEAT_NUM_QUEUES	0x07
RT_NVME_FEAT_IRQ_COALESCE	0x08
RT_NVME_FEAT_IRQ_CONFIG	0x09
RT_NVME_FEAT_WRITE_ATOMIC	0x0a
RT_NVME_FEAT_ASYNC_EVENT	0x0b
RT_NVME_FEAT_AUTO_PST	0x0c
RT_NVME_FEAT_SW_PROGRESS	0x80
RT_NVME_FEAT_HOST_ID	0x81
RT_NVME_FEAT_RESV_MASK	0x82
RT_NVME_FEAT_RESV_PERSIST	0x83
RT_NVME_LOG_ERROR	0x01
RT_NVME_LOG_SMART	0x02
RT_NVME_LOG_FW_SLOT	0x03
RT_NVME_LOG_RESERVATION	0x80
RT_NVME_FWACT_REPL	(0 << 3)
RT_NVME_FWACT_REPL_ACTV	(1 << 3)
RT_NVME_FWACT_ACTV	(2 << 3)

在文件 nvme.h 第 319 行定义.

{
    RT_NVME_QUEUE_PHYS_CONTIG   = (1 << 0),
    RT_NVME_CQ_IRQ_ENABLED      = (1 << 1),
    RT_NVME_SQ_PRIO_URGENT      = (0 << 1),
    RT_NVME_SQ_PRIO_HIGH        = (1 << 1),
    RT_NVME_SQ_PRIO_MEDIUM      = (2 << 1),
    RT_NVME_SQ_PRIO_LOW         = (3 << 1),
    RT_NVME_FEAT_ARBITRATION    = 0x01,
    RT_NVME_FEAT_POWER_MGMT     = 0x02,
    RT_NVME_FEAT_LBA_RANGE      = 0x03,
    RT_NVME_FEAT_TEMP_THRESH    = 0x04,
    RT_NVME_FEAT_ERR_RECOVERY   = 0x05,
    RT_NVME_FEAT_VOLATILE_WC    = 0x06,
    RT_NVME_FEAT_NUM_QUEUES     = 0x07,
    RT_NVME_FEAT_IRQ_COALESCE   = 0x08,
    RT_NVME_FEAT_IRQ_CONFIG     = 0x09,
    RT_NVME_FEAT_WRITE_ATOMIC   = 0x0a,
    RT_NVME_FEAT_ASYNC_EVENT    = 0x0b,
    RT_NVME_FEAT_AUTO_PST       = 0x0c,
    RT_NVME_FEAT_SW_PROGRESS    = 0x80,
    RT_NVME_FEAT_HOST_ID        = 0x81,
    RT_NVME_FEAT_RESV_MASK      = 0x82,
    RT_NVME_FEAT_RESV_PERSIST   = 0x83,
    RT_NVME_LOG_ERROR           = 0x01,
    RT_NVME_LOG_SMART           = 0x02,
    RT_NVME_LOG_FW_SLOT         = 0x03,
    RT_NVME_LOG_RESERVATION     = 0x80,
    RT_NVME_FWACT_REPL          = (0 << 3),
    RT_NVME_FWACT_REPL_ACTV     = (1 << 3),
    RT_NVME_FWACT_ACTV          = (2 << 3),
};

anonymous enum

anonymous enum

枚举值
RT_NVME_REG_CAP	0x0000
RT_NVME_REG_VS	0x0008
RT_NVME_REG_INTMS	0x000c
RT_NVME_REG_INTMC	0x0010
RT_NVME_REG_CC	0x0014
RT_NVME_REG_CSTS	0x001c
RT_NVME_REG_NSSR	0x0020
RT_NVME_REG_AQA	0x0024
RT_NVME_REG_ASQ	0x0028
RT_NVME_REG_ACQ	0x0030
RT_NVME_REG_CMBLOC	0x0038
RT_NVME_REG_CMBSZ	0x003c
RT_NVME_REG_BPINFO	0x0040
RT_NVME_REG_BPRSEL	0x0044
RT_NVME_REG_BPMBL	0x0048
RT_NVME_REG_CMBMSC	0x0050
RT_NVME_REG_CRTO	0x0068
RT_NVME_REG_PMRCAP	0x0e00
RT_NVME_REG_PMRCTL	0x0e04
RT_NVME_REG_PMRSTS	0x0e08
RT_NVME_REG_PMREBS	0x0e0c
RT_NVME_REG_PMRSWTP	0x0e10
RT_NVME_REG_DBS	0x1000

在文件 nvme.h 第 467 行定义.

{
    RT_NVME_REG_CAP         = 0x0000,   /* Controller Capabilities */
    RT_NVME_REG_VS          = 0x0008,   /* Version */
    RT_NVME_REG_INTMS       = 0x000c,   /* Interrupt Mask Set */
    RT_NVME_REG_INTMC       = 0x0010,   /* Interrupt Mask Clear */
    RT_NVME_REG_CC          = 0x0014,   /* Controller Configuration */
    RT_NVME_REG_CSTS        = 0x001c,   /* Controller Status */
    RT_NVME_REG_NSSR        = 0x0020,   /* NVM Subsystem Reset */
    RT_NVME_REG_AQA         = 0x0024,   /* Admin Queue Attributes */
    RT_NVME_REG_ASQ         = 0x0028,   /* Admin SQ Base Address */
    RT_NVME_REG_ACQ         = 0x0030,   /* Admin CQ Base Address */
    RT_NVME_REG_CMBLOC      = 0x0038,   /* Controller Memory Buffer Location */
    RT_NVME_REG_CMBSZ       = 0x003c,   /* Controller Memory Buffer Size */
    RT_NVME_REG_BPINFO      = 0x0040,   /* Boot Partition Information */
    RT_NVME_REG_BPRSEL      = 0x0044,   /* Boot Partition Read Select */
    RT_NVME_REG_BPMBL       = 0x0048,   /* Boot Partition Memory Buffer Location */
    RT_NVME_REG_CMBMSC      = 0x0050,   /* Controller Memory Buffer Memory Space Control */
    RT_NVME_REG_CRTO        = 0x0068,   /* Controller Ready Timeouts */
    RT_NVME_REG_PMRCAP      = 0x0e00,   /* Persistent Memory Capabilities */
    RT_NVME_REG_PMRCTL      = 0x0e04,   /* Persistent Memory Region Control */
    RT_NVME_REG_PMRSTS      = 0x0e08,   /* Persistent Memory Region Status */
    RT_NVME_REG_PMREBS      = 0x0e0c,   /* Persistent Memory Region Elasticity Buffer Size */
    RT_NVME_REG_PMRSWTP     = 0x0e10,   /* Persistent Memory Region Sustained Write Throughput */
    RT_NVME_REG_DBS         = 0x1000,   /* SQ 0 Tail Doorbell */
};

anonymous enum

anonymous enum

枚举值
RT_NVME_CC_ENABLE	1 << 0
RT_NVME_CC_CSS_NVM	0 << 4
RT_NVME_CC_MPS_SHIFT	7
RT_NVME_CC_ARB_RR	0 << 11
RT_NVME_CC_ARB_WRRU	1 << 11
RT_NVME_CC_ARB_VS	7 << 11
RT_NVME_CC_SHN_NONE	0 << 14
RT_NVME_CC_SHN_NORMAL	1 << 14
RT_NVME_CC_SHN_ABRUPT	2 << 14
RT_NVME_CC_SHN_MASK	3 << 14
RT_NVME_CC_IOSQES	6 << 16
RT_NVME_CC_IOCQES	4 << 20
RT_NVME_CSTS_RDY	1 << 0
RT_NVME_CSTS_CFS	1 << 1
RT_NVME_CSTS_SHST_NORMAL	0 << 2
RT_NVME_CSTS_SHST_OCCUR	1 << 2
RT_NVME_CSTS_SHST_CMPLT	2 << 2
RT_NVME_CSTS_SHST_MASK	3 << 2

在文件 nvme.h 第 507 行定义.

{
    RT_NVME_CC_ENABLE           = 1 << 0,
    RT_NVME_CC_CSS_NVM          = 0 << 4,
    RT_NVME_CC_MPS_SHIFT        = 7,
    RT_NVME_CC_ARB_RR           = 0 << 11,
    RT_NVME_CC_ARB_WRRU         = 1 << 11,
    RT_NVME_CC_ARB_VS           = 7 << 11,
    RT_NVME_CC_SHN_NONE         = 0 << 14,
    RT_NVME_CC_SHN_NORMAL       = 1 << 14,
    RT_NVME_CC_SHN_ABRUPT       = 2 << 14,
    RT_NVME_CC_SHN_MASK         = 3 << 14,
    RT_NVME_CC_IOSQES           = 6 << 16,
    RT_NVME_CC_IOCQES           = 4 << 20,
    RT_NVME_CSTS_RDY            = 1 << 0,
    RT_NVME_CSTS_CFS            = 1 << 1,
    RT_NVME_CSTS_SHST_NORMAL    = 0 << 2,
    RT_NVME_CSTS_SHST_OCCUR     = 1 << 2,
    RT_NVME_CSTS_SHST_CMPLT     = 2 << 2,
    RT_NVME_CSTS_SHST_MASK      = 3 << 2,
};

anonymous enum

anonymous enum

枚举值
RT_NVME_CTRL_CMIC_MULTI_PORT	1 << 0
RT_NVME_CTRL_CMIC_MULTI_CTRL	1 << 1
RT_NVME_CTRL_CMIC_ANA	1 << 3
RT_NVME_CTRL_ONCS_COMPARE	1 << 0
RT_NVME_CTRL_ONCS_WRITE_UNCORRECTABLE	1 << 1
RT_NVME_CTRL_ONCS_DSM	1 << 2
RT_NVME_CTRL_ONCS_WRITE_ZEROES	1 << 3
RT_NVME_CTRL_ONCS_RESERVATIONS	1 << 5
RT_NVME_CTRL_ONCS_TIMESTAMP	1 << 6
RT_NVME_CTRL_VWC_PRESENT	1 << 0
RT_NVME_CTRL_OACS_SEC_SUPP	1 << 0
RT_NVME_CTRL_OACS_NS_MNGT_SUPP	1 << 3
RT_NVME_CTRL_OACS_DIRECTIVES	1 << 5
RT_NVME_CTRL_OACS_DBBUF_SUPP	1 << 8
RT_NVME_CTRL_LPA_CMD_EFFECTS_LOG	1 << 1
RT_NVME_CTRL_CTRATT_128_ID	1 << 0
RT_NVME_CTRL_CTRATT_NON_OP_PSP	1 << 1
RT_NVME_CTRL_CTRATT_NVM_SETS	1 << 2
RT_NVME_CTRL_CTRATT_READ_RECV_LVLS	1 << 3
RT_NVME_CTRL_CTRATT_ENDURANCE_GROUPS	1 << 4
RT_NVME_CTRL_CTRATT_PREDICTABLE_LAT	1 << 5
RT_NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY	1 << 7
RT_NVME_CTRL_CTRATT_UUID_LIST	1 << 9

在文件 nvme.h 第 693 行定义.

{
    RT_NVME_CTRL_CMIC_MULTI_PORT                = 1 << 0,
    RT_NVME_CTRL_CMIC_MULTI_CTRL                = 1 << 1,
    RT_NVME_CTRL_CMIC_ANA                       = 1 << 3,
    RT_NVME_CTRL_ONCS_COMPARE                   = 1 << 0,
    RT_NVME_CTRL_ONCS_WRITE_UNCORRECTABLE       = 1 << 1,
    RT_NVME_CTRL_ONCS_DSM                       = 1 << 2,
    RT_NVME_CTRL_ONCS_WRITE_ZEROES              = 1 << 3,
    RT_NVME_CTRL_ONCS_RESERVATIONS              = 1 << 5,
    RT_NVME_CTRL_ONCS_TIMESTAMP                 = 1 << 6,
    RT_NVME_CTRL_VWC_PRESENT                    = 1 << 0,
    RT_NVME_CTRL_OACS_SEC_SUPP                  = 1 << 0,
    RT_NVME_CTRL_OACS_NS_MNGT_SUPP              = 1 << 3,
    RT_NVME_CTRL_OACS_DIRECTIVES                = 1 << 5,
    RT_NVME_CTRL_OACS_DBBUF_SUPP                = 1 << 8,
    RT_NVME_CTRL_LPA_CMD_EFFECTS_LOG            = 1 << 1,
    RT_NVME_CTRL_CTRATT_128_ID                  = 1 << 0,
    RT_NVME_CTRL_CTRATT_NON_OP_PSP              = 1 << 1,
    RT_NVME_CTRL_CTRATT_NVM_SETS                = 1 << 2,
    RT_NVME_CTRL_CTRATT_READ_RECV_LVLS          = 1 << 3,
    RT_NVME_CTRL_CTRATT_ENDURANCE_GROUPS        = 1 << 4,
    RT_NVME_CTRL_CTRATT_PREDICTABLE_LAT         = 1 << 5,
    RT_NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY   = 1 << 7,
    RT_NVME_CTRL_CTRATT_UUID_LIST               = 1 << 9,
};

anonymous enum

anonymous enum

枚举值
RT_NVME_NS_FEAT_THIN	1 << 0
RT_NVME_NS_FLBAS_LBA_MASK	0xf
RT_NVME_NS_FLBAS_LBA_UMASK	0x60
RT_NVME_NS_FLBAS_LBA_SHIFT	1
RT_NVME_NS_FLBAS_META_EXT	0x10
RT_NVME_LBAF_RP_BEST	0
RT_NVME_LBAF_RP_BETTER	1
RT_NVME_LBAF_RP_GOOD	2
RT_NVME_LBAF_RP_DEGRADED	3
RT_NVME_NS_DPC_PI_LAST	1 << 4
RT_NVME_NS_DPC_PI_FIRST	1 << 3
RT_NVME_NS_DPC_PI_TYPE3	1 << 2
RT_NVME_NS_DPC_PI_TYPE2	1 << 1
RT_NVME_NS_DPC_PI_TYPE1	1 << 0
RT_NVME_NS_DPS_PI_FIRST	1 << 3
RT_NVME_NS_DPS_PI_MASK	0x7
RT_NVME_NS_DPS_PI_TYPE1	1
RT_NVME_NS_DPS_PI_TYPE2	2
RT_NVME_NS_DPS_PI_TYPE3	3

在文件 nvme.h 第 772 行定义.

{
    RT_NVME_NS_FEAT_THIN        = 1 << 0,
    RT_NVME_NS_FLBAS_LBA_MASK   = 0xf,
    RT_NVME_NS_FLBAS_LBA_UMASK  = 0x60,
    RT_NVME_NS_FLBAS_LBA_SHIFT  = 1,
    RT_NVME_NS_FLBAS_META_EXT   = 0x10,
    RT_NVME_LBAF_RP_BEST        = 0,
    RT_NVME_LBAF_RP_BETTER      = 1,
    RT_NVME_LBAF_RP_GOOD        = 2,
    RT_NVME_LBAF_RP_DEGRADED    = 3,
    RT_NVME_NS_DPC_PI_LAST      = 1 << 4,
    RT_NVME_NS_DPC_PI_FIRST     = 1 << 3,
    RT_NVME_NS_DPC_PI_TYPE3     = 1 << 2,
    RT_NVME_NS_DPC_PI_TYPE2     = 1 << 1,
    RT_NVME_NS_DPC_PI_TYPE1     = 1 << 0,
    RT_NVME_NS_DPS_PI_FIRST     = 1 << 3,
    RT_NVME_NS_DPS_PI_MASK      = 0x7,
    RT_NVME_NS_DPS_PI_TYPE1     = 1,
    RT_NVME_NS_DPS_PI_TYPE2     = 2,
    RT_NVME_NS_DPS_PI_TYPE3     = 3,
};

函数说明

rt_packed() [1/4]

rt_packed

(

struct rt_nvme_sgl_desc { rt_le64_t adddress;rt_le32_t length;rt_uint8_t reserved[3];#define SGL_DESC_TYPE_DATA_BLOCK #define SGL_DESC_TYPE_BIT_BUCKET #define SGL_DESC_TYPE_SEGMENT #define SGL_DESC_TYPE_LAST_SEGMENT #define SGL_DESC_TYPE_KEYED_DATA_BLOCK #define SGL_DESC_TYPE_VENDOR_SPECIFIC rt_uint8_t sgl_identify;}

)

rt_packed() [2/4]

rt_packed

(

struct rt_nvme_id_power_state { rt_le16_t mp;NVME_RSVD(1, 1);rt_uint8_t mxps_nops;rt_le32_t enlat;rt_le32_t exlat;rt_uint8_t rrt;rt_uint8_t rrl;rt_uint8_t rwt;rt_uint8_t rwl;rt_le16_t idlp;rt_uint8_t ips;NVME_RSVD(19, 1);rt_le16_t actp;rt_uint8_t apw_aps;NVME_RSVD(23, 9);}

)

引用了 NVME_RSVD.

rt_packed() [3/4]

rt_packed

(

struct rt_nvme_id_ctrl { rt_le16_t vid;rt_le16_t ssvid;char sn[20];char mn[40];char fr[8];rt_uint8_t rab;rt_uint8_t ieee[3];rt_uint8_t mic;rt_uint8_t mdts;rt_uint16_t cntlid;rt_uint32_t ver;rt_uint32_t rtd3r;rt_uint32_t rtd3e;rt_uint32_t oaes;#define RT_NVME_ID_CTRATT_ELBAS #define RT_NVME_ID_CTRATT_DNVMS #define RT_NVME_ID_CTRATT_DEG #define RT_NVME_ID_CTRATT_VCM #define RT_NVME_ID_CTRATT_FCM #define RT_NVME_ID_CTRATT_MDS #define RT_NVME_ID_CTRATT_UUIDL #define RT_NVME_ID_CTRATT_SQA #define RT_NVME_ID_CTRATT_NG #define RT_NVME_ID_CTRATT_TBKAS #define RT_NVME_ID_CTRATT_PLM #define RT_NVME_ID_CTRATT_EG #define RT_NVME_ID_CTRATT_RRL #define RT_NVME_ID_CTRATT_NVMS #define RT_NVME_ID_CTRATT_NOPSPM #define RT_NVME_ID_CTRATT_HIS rt_uint32_t ctratt;rt_uint16_t rrls;NVME_RSVD(102, 9);rt_uint8_t cntrltype;rt_uint8_t fguid[16];rt_uint16_t crdt1;rt_uint16_t crdt2;rt_uint16_t crdt3;NVME_RSVD(134, 119);#define RT_NVME_ID_NVMSR_NVMEE #define RT_NVME_ID_NVMSR_NVMESD rt_uint8_t nvmsr;#define RT_NVME_ID_VWCI_VWCRV #define RT_NVME_ID_VWCI_VWCR rt_uint8_t vwci;#define RT_NVME_ID_MEC_PCIEME #define RT_NVME_ID_MEC_SMBUSME rt_uint8_t mec;rt_le16_t oacs;rt_uint8_t acl;rt_uint8_t aerl;#define RT_NVME_ID_FRMW_SMUD #define RT_NVME_ID_FRMW_FAWR #define RT_NVME_ID_FRMW_NOFS #define RT_NVME_ID_FRMW_FFSRO rt_uint8_t frmw;rt_uint8_t lpa;rt_uint8_t elpe;rt_uint8_t npss;rt_uint8_t avscc;rt_uint8_t apsta;rt_le16_t wctemp;rt_le16_t cctemp;rt_uint16_t mtfa;rt_uint32_t hmpre;rt_uint32_t hmmin;rt_uint8_t tnvmcap[16];rt_uint8_t unvmcap[16];#define RT_NVME_ID_RPMBS_ASZ #define RT_NVME_ID_RPMBS_TSZ #define RT_NVME_ID_RPMBS_AM #define RT_NVME_ID_RPMBS_NORPMBU rt_uint32_t rpmbs;rt_uint16_t edstt;rt_uint8_t dsto;rt_uint8_t fwug;rt_uint16_t kas;rt_uint16_t hctma;rt_uint16_t mntmt;rt_uint16_t mxtmt;#define RT_NVME_ID_SANICAP_NODMMAS #define RT_NVME_ID_SANICAP_NDI #define RT_NVME_ID_SANICAP_OWS #define RT_NVME_ID_SANICAP_BES #define RT_NVME_ID_SANICAP_CES rt_uint32_t sanicap;rt_uint32_t hmminds;rt_uint16_t hmmaxd;rt_uint16_t nsetidmax;rt_uint16_t endgidmax;rt_uint8_t anatt;rt_uint8_t anacap;rt_uint32_t anagrpmax;rt_uint32_t nanagrpid;rt_uint32_t pels;rt_uint16_t dmid;NVME_RSVD(358, 10);rt_uint8_t megcap[16];NVME_RSVD(384, 128);rt_uint8_t sqes;rt_uint8_t cqes;rt_le16_t maxcmd;rt_le32_t nn;rt_le16_t oncs;rt_le16_t fuses;rt_uint8_t fna;rt_uint8_t vwc;rt_le16_t awun;rt_le16_t awupf;rt_uint8_t nvscc;rt_uint8_t nwpc;rt_le16_t acwu;rt_le16_t cdfs;#define RT_NVME_ID_SGL_SUPPORT_MASK rt_le32_t sgls;rt_uint32_t mnan;char maxdna[16];rt_le32_t maxcna;NVME_RSVD(564, 204);rt_uint8_t subnqn[256];NVME_RSVD(1024, 768);rt_le32_t ioccsz;rt_le32_t iorcsz;rt_le16_t icdoff;rt_uint8_t ctrattr;rt_uint8_t msdbd;rt_le16_t ofcs;rt_uint8_t dctype;NVME_RSVD(1807, 241);struct rt_nvme_id_power_state psd[32];rt_uint8_t vs[1024];}

)

引用了 NVME_RSVD.

rt_packed() [4/4]

rt_packed

(

struct rt_nvme_id_ns { rt_le64_t nsze;rt_le64_t ncap;rt_le64_t nuse;rt_uint8_t nsfeat;rt_uint8_t nlbaf;rt_uint8_t flbas;rt_uint8_t mc;rt_uint8_t dpc;rt_uint8_t dps;rt_uint8_t nmic;rt_uint8_t rescap;rt_uint8_t fpi;rt_uint8_t dlfeat;rt_le16_t nawun;rt_le16_t nawupf;rt_le16_t nacwu;rt_le16_t nabsn;rt_le16_t nabo;rt_le16_t nabspf;rt_uint16_t noiob;rt_le64_t nvmcap[2];rt_uint16_t npwg;rt_uint16_t npwa;rt_uint16_t npdg;rt_uint16_t npda;rt_uint16_t nows;NVME_RSVD(118, 18);rt_uint32_t anagrpid;NVME_RSVD(139, 3);rt_uint8_t nsattr;rt_uint16_t nvmsetid;rt_uint16_t endgid;rt_uint8_t nguid[16];rt_uint8_t eui64[8];struct rt_nvme_lba_format lbaf[16];NVME_RSVD(171, 192);rt_uint8_t vs[3712];}

)

引用了 NVME_RSVD.

rt_nvme_controller_register()

rt_err_t rt_nvme_controller_register

(

struct rt_nvme_controller *

nvme

)

rt_nvme_controller_unregister()

rt_err_t rt_nvme_controller_unregister

(

struct rt_nvme_controller *

nvme

)