#include <rthw.h>
#include <rtthread.h>
#include <drivers/scsi.h>
#include <drivers/misc.h>

ahci.h 的引用(Include)关系图:

结构体
struct	rt_ahci_cmd_hdr

struct	rt_ahci_sg

struct	rt_ahci_port

struct	rt_ahci_host

struct	rt_ahci_ops

宏定义
#define	RT_AHCI_HBA_CAP 0x00 /* Host capability*/

#define	RT_AHCI_CAP_NP RT_GENMASK(4, 0) /* Number of Ports */

#define	RT_AHCI_CAP_NCS RT_GENMASK(8, 12) /* Number of Command Slots */

#define	RT_AHCI_CAP_PSC RT_BIT(13) /* Partial State Capable */

#define	RT_AHCI_CAP_SSC RT_BIT(14) /* Slumber capable */

#define	RT_AHCI_CAP_PMD RT_BIT(15) /* PIO Multiple DRQ Block */

#define	RT_AHCI_CAP_SPM RT_BIT(17) /* Port Multiplier */

#define	RT_AHCI_CAP_AHCI RT_BIT(18) /* AHCI only */

#define	RT_AHCI_CAP_SNZO RT_BIT(19) /* Non-Zero DMA Offsets */

#define	RT_AHCI_CAP_ISS RT_GENMASK(23, 20) /* Interface Speed Support */

#define	RT_AHCI_CAP_CLO RT_BIT(24) /* Command List Override support */

#define	RT_AHCI_CAP_SAL RT_BIT(25) /* Activity LED */

#define	RT_AHCI_CAP_SALP RT_BIT(26) /* Aggressive Link Power Management */

#define	RT_AHCI_CAP_SSS RT_BIT(27) /* Staggered Spin-up */

#define	RT_AHCI_CAP_SIS RT_BIT(28) /* Interlock Switch */

#define	RT_AHCI_CAP_NCQ RT_BIT(30) /* Native Command Queueing */

#define	RT_AHCI_CAP_64 RT_BIT(31) /* PCI DAC (64-bit DMA) support */

#define	RT_AHCI_HBA_GHC 0x04 /* Global host control */

#define	RT_AHCI_GHC_RESET RT_BIT(0) /* Reset controller; self-clear */

#define	RT_AHCI_GHC_IRQ_EN RT_BIT(1) /* Global IRQ enable */

#define	RT_AHCI_GHC_AHCI_EN RT_BIT(31) /* AHCI enabled */

#define	RT_AHCI_HBA_INTS 0x08 /* Interrupt status */

#define	RT_AHCI_HBA_PI 0x0c /* Port implemented */

#define	RT_AHCI_HBA_VS 0x10 /* Version */

#define	RT_AHCI_HBA_CCC_CTL 0x14 /* Command completion coalescing control */

#define	RT_AHCI_HBA_CCC_PTS 0x18 /* Command completion coalescing ports */

#define	RT_AHCI_HBA_EM_LOC 0x1c /* Enclosure management location */

#define	RT_AHCI_HBA_EM_CTL 0x20 /* Enclosure management control */

#define	RT_AHCI_HBA_CAP2 0x24 /* Host capabilities extended */

#define	RT_AHCI_HBA_BOHC 0x28 /* BIOS/OS handoff control and status */

#define	RT_AHCI_HBA_VENDOR 0xa0 /* Vendor specific registers (0xa0 - 0xff) */

#define	RT_AHCI_PORT_CLB 0x00 /* Command list base address, 1K-byte aligned */

#define	RT_AHCI_PORT_CLBU 0x04 /* Command list base address upper 32 bits */

#define	RT_AHCI_PORT_FB 0x08 /* FIS base address, 256-byte aligned */

#define	RT_AHCI_PORT_FBU 0x0C /* FIS base address upper 32 bits */

#define	RT_AHCI_PORT_INTS 0x10 /* Interrupt status */

#define	RT_AHCI_PORT_INTE 0x14 /* Interrupt enable */

#define	RT_AHCI_PORT_INTE_D2H_REG_FIS RT_BIT(0) /* D2H Register FIS rx'd */

#define	RT_AHCI_PORT_INTE_PIOS_FIS RT_BIT(1) /* PIO Setup FIS rx'd */

#define	RT_AHCI_PORT_INTE_DMAS_FIS RT_BIT(2) /* DMA Setup FIS rx'd */

#define	RT_AHCI_PORT_INTE_SDB_FIS RT_BIT(3) /* Set Device Bits FIS rx'd */

#define	RT_AHCI_PORT_INTE_UNK_FIS RT_BIT(4) /* Unknown FIS rx'd */

#define	RT_AHCI_PORT_INTE_SG_DONE RT_BIT(5) /* Descriptor processed */

#define	RT_AHCI_PORT_INTE_CONNECT RT_BIT(6) /* Port connect change status */

#define	RT_AHCI_PORT_INTE_DMPS RT_BIT(7) /* Mechanical presence status */

#define	RT_AHCI_PORT_INTE_PHYRDY RT_BIT(22) /* PhyRdy changed */

#define	RT_AHCI_PORT_INTE_BAD_PMP RT_BIT(23) /* Incorrect port multiplier */

#define	RT_AHCI_PORT_INTE_OVERFLOW RT_BIT(24) /* Xfer exhausted available S/G */

#define	RT_AHCI_PORT_INTE_IF_NONFATAL RT_BIT(26) /* Interface non-fatal error */

#define	RT_AHCI_PORT_INTE_IF_ERR RT_BIT(27) /* Interface fatal error */

#define	RT_AHCI_PORT_INTE_HBUS_DATA_ERR RT_BIT(28) /* Host bus data error */

#define	RT_AHCI_PORT_INTE_HBUS_ERR RT_BIT(29) /* Host bus fatal error */

#define	RT_AHCI_PORT_INTE_TF_ERR RT_BIT(30) /* Task file error */

#define	RT_AHCI_PORT_INTE_COLD_PRES RT_BIT(31) /* Cold presence detect */

#define	RT_AHCI_PORT_CMD 0x18 /* Command and status */

#define	RT_AHCI_PORT_CMD_START RT_BIT(0) /* Enable port DMA engine */

#define	RT_AHCI_PORT_CMD_SPIN_UP RT_BIT(1) /* Spin up device */

#define	RT_AHCI_PORT_CMD_POWER_ON RT_BIT(2) /* Power up device */

#define	RT_AHCI_PORT_CMD_CLO RT_BIT(3) /* Command list override */

#define	RT_AHCI_PORT_CMD_FIS_RX RT_BIT(4) /* Enable FIS receive DMA engine */

#define	RT_AHCI_PORT_CMD_FIS_ON RT_BIT(14) /* FIS DMA engine running */

#define	RT_AHCI_PORT_CMD_LIST_ON RT_BIT(15) /* cmd list DMA engine running */

#define	RT_AHCI_PORT_CMD_ATAPI RT_BIT(24) /* Device is ATAPI */

#define	RT_AHCI_PORT_CMD_ACTIVE RT_BIT(28) /* Active state */

#define	RT_AHCI_PORT_TFD 0x20 /* Task file data */

#define	RT_AHCI_PORT_TFDATA_ERR RT_BIT(0) /* Indicates an error during the transfer */

#define	RT_AHCI_PORT_TFDATA_DRQ RT_BIT(3) /* Indicates a data transfer is requested */

#define	RT_AHCI_PORT_TFDATA_BSY RT_BIT(7) /* Indicates the interface is busy */

#define	RT_AHCI_PORT_SIG 0x24 /* Signature */

#define	RT_AHCI_PORT_SIG_REG_MASK 0xff

#define	RT_AHCI_PORT_SIG_SECTOR_NR_SHIFT 0 /* Sector Count Register */

#define	RT_AHCI_PORT_SIG_LBA_LOW_SHIFT 8 /* LBA Low Register */

#define	RT_AHCI_PORT_SIG_LBA_MID_SHIFT 16 /* LBA Mid Register */

#define	RT_AHCI_PORT_SIG_LBA_HIGH_SHIFT 24 /* LBA High Register */

#define	RT_AHCI_PORT_SIG_SATA_CDROM 0xeb140101

#define	RT_AHCI_PORT_SIG_SATA_DISK 0x00000101

#define	RT_AHCI_PORT_SSTS 0x28 /* SATA status (SCR0:SStatus) */

#define	RT_AHCI_PORT_SSTS_DET_MASK 0x3

#define	RT_AHCI_PORT_SSTS_DET_COMINIT 0x1

#define	RT_AHCI_PORT_SSTS_DET_PHYRDY 0x3

#define	RT_AHCI_PORT_SCTL 0x2c /* SATA control (SCR2:SControl) */

#define	RT_AHCI_PORT_SERR 0x30 /* SATA error (SCR1:SError) */

#define	RT_AHCI_PORT_SERR_ERR_I RT_BIT(0) /* Recovered Data Integrity Error */

#define	RT_AHCI_PORT_SERR_ERR_M RT_BIT(1) /* Recovered Communications Error */

#define	RT_AHCI_PORT_SERR_ERR_T RT_BIT(8) /* Transient Data Integrity Error */

#define	RT_AHCI_PORT_SERR_ERR_C RT_BIT(9) /* Persistent Communication or Data Integrity Error */

#define	RT_AHCI_PORT_SERR_ERR_P RT_BIT(10) /* Protocol Error */

#define	RT_AHCI_PORT_SERR_ERR_E RT_BIT(11) /* Internal Error */

#define	RT_AHCI_PORT_SERR_DIAG_N RT_BIT(16) /* PhyRdy Change */

#define	RT_AHCI_PORT_SERR_DIAG_I RT_BIT(17) /* Phy Internal Error */

#define	RT_AHCI_PORT_SERR_DIAG_W RT_BIT(18) /* Comm Wake */

#define	RT_AHCI_PORT_SERR_DIAG_B RT_BIT(19) /* 10B to 8B Decode Error */

#define	RT_AHCI_PORT_SERR_DIAG_D RT_BIT(20) /* Disparity Error */

#define	RT_AHCI_PORT_SERR_DIAG_C RT_BIT(21) /* CRC Error */

#define	RT_AHCI_PORT_SERR_DIAG_H RT_BIT(22) /* Handshake Error */

#define	RT_AHCI_PORT_SERR_DIAG_S RT_BIT(23) /* Link Sequence Error */

#define	RT_AHCI_PORT_SERR_DIAG_T RT_BIT(24) /* Transport state transition error */

#define	RT_AHCI_PORT_SERR_DIAG_F RT_BIT(25) /* Unknown FIS Type */

#define	RT_AHCI_PORT_SERR_DIAG_X RT_BIT(26) /* Exchanged */

#define	RT_AHCI_PORT_SACT 0x34 /* SATA active (SCR3:SActive) */

#define	RT_AHCI_PORT_CI 0x38 /* Command issue */

#define	RT_AHCI_PORT_SNTF 0x3c /* SATA notification (SCR4:SNotification) */

#define	RT_AHCI_PORT_FBS 0x40 /* FIS-based switch control */

#define	RT_AHCI_PORT_VENDOR 0x70 /* Vendor specific (0x70 - 0x7f) */

#define	RT_AHCI_MAX_SG 56

#define	RT_AHCI_CMD_SLOT_SIZE 32

#define	RT_AHCI_MAX_CMD_SLOT 32

#define	RT_AHCI_RX_FIS_SIZE 256

#define	RT_AHCI_CMD_TBL_HDR 0x80

#define	RT_AHCI_CMD_TBL_CDB 0x40

#define	RT_AHCI_CMD_TBL_SIZE RT_AHCI_CMD_TBL_HDR + (RT_AHCI_MAX_SG * 16)

#define	RT_AHCI_DMA_SIZE (RT_AHCI_CMD_SLOT_SIZE * RT_AHCI_MAX_CMD_SLOT + RT_AHCI_CMD_TBL_SIZE + RT_AHCI_RX_FIS_SIZE)

#define	RT_ACHI_PRDT_BYTES_MAX (4 * 1024 * 1024)

#define	RT_AHCI_FIS_TYPE_REG_H2D 0x27 /* Register FIS - host to device */

#define	RT_AHCI_FIS_TYPE_REG_D2H 0x34 /* Register FIS - device to host */

#define	RT_AHCI_FIS_TYPE_DMA_ACT 0x39 /* DMA activate FIS - device to host */

#define	RT_AHCI_FIS_TYPE_DMA_SETUP 0x41 /* DMA setup FIS - bidirectional */

#define	RT_AHCI_FIS_TYPE_DATA 0x46 /* Data FIS - bidirectional */

#define	RT_AHCI_FIS_TYPE_BIST 0x58 /* BIST activate FIS - bidirectional */

#define	RT_AHCI_FIS_TYPE_PIO_SETUP 0x5f /* PIO setup FIS - device to host */

#define	RT_AHCI_FIS_TYPE_DEV_BITS 0xa1 /* Set device bits FIS - device to host */

#define	RT_AHCI_ATA_ID_WORDS 256

#define	RT_AHCI_ATA_ID_CONFIG 0

#define	RT_AHCI_ATA_ID_CYLS 1

#define	RT_AHCI_ATA_ID_HEADS 3

#define	RT_AHCI_ATA_ID_SECTORS 6

#define	RT_AHCI_ATA_ID_SERNO 10

#define	RT_AHCI_ATA_ID_BUF_SIZE 21

#define	RT_AHCI_ATA_ID_FW_REV 23

#define	RT_AHCI_ATA_ID_PROD 27

#define	RT_AHCI_ATA_ID_MAX_MULTSECT 47

#define	RT_AHCI_ATA_ID_DWORD_IO 48

#define	RT_AHCI_ATA_ID_TRUSTED 48

#define	RT_AHCI_ATA_ID_CAPABILITY 49

#define	RT_AHCI_ATA_ID_OLD_PIO_MODES 51

#define	RT_AHCI_ATA_ID_OLD_DMA_MODES 52

#define	RT_AHCI_ATA_ID_FIELD_VALID 53

#define	RT_AHCI_ATA_ID_CUR_CYLS 54

#define	RT_AHCI_ATA_ID_CUR_HEADS 55

#define	RT_AHCI_ATA_ID_CUR_SECTORS 56

#define	RT_AHCI_ATA_ID_MULTSECT 59

#define	RT_AHCI_ATA_ID_LBA_CAPACITY 60

#define	RT_AHCI_ATA_ID_SWDMA_MODES 62

#define	RT_AHCI_ATA_ID_MWDMA_MODES 63

#define	RT_AHCI_ATA_ID_PIO_MODES 64

#define	RT_AHCI_ATA_ID_EIDE_DMA_MIN 65

#define	RT_AHCI_ATA_ID_EIDE_DMA_TIME 66

#define	RT_AHCI_ATA_ID_EIDE_PIO 67

#define	RT_AHCI_ATA_ID_EIDE_PIO_IORDY 68

#define	RT_AHCI_ATA_ID_ADDITIONAL_SUPP 69

#define	RT_AHCI_ATA_ID_QUEUE_DEPTH 75

#define	RT_AHCI_ATA_ID_SATA_CAPABILITY 76

#define	RT_AHCI_ATA_ID_SATA_CAPABILITY_2 77

#define	RT_AHCI_ATA_ID_FEATURE_SUPP 78

#define	RT_AHCI_ATA_ID_MAJOR_VER 80

#define	RT_AHCI_ATA_ID_COMMAND_SET_1 82

#define	RT_AHCI_ATA_ID_COMMAND_SET_2 83

#define	RT_AHCI_ATA_ID_CFSSE 84

#define	RT_AHCI_ATA_ID_CFS_ENABLE_1 85

#define	RT_AHCI_ATA_ID_CFS_ENABLE_2 86

#define	RT_AHCI_ATA_ID_CSF_DEFAULT 87

#define	RT_AHCI_ATA_ID_UDMA_MODES 88

#define	RT_AHCI_ATA_ID_HW_CONFIG 93

#define	RT_AHCI_ATA_ID_SPG 98

#define	RT_AHCI_ATA_ID_LBA_CAPACITY_2 100

#define	RT_AHCI_ATA_ID_SECTOR_SIZE 106

#define	RT_AHCI_ATA_ID_WWN 108

#define	RT_AHCI_ATA_ID_LOGICAL_SECTOR_SIZE 117

#define	RT_AHCI_ATA_ID_COMMAND_SET_3 119

#define	RT_AHCI_ATA_ID_COMMAND_SET_4 120

#define	RT_AHCI_ATA_ID_LAST_LUN 126

#define	RT_AHCI_ATA_ID_DLF 128

#define	RT_AHCI_ATA_ID_CSFO 129

#define	RT_AHCI_ATA_ID_CFA_POWER 160

#define	RT_AHCI_ATA_ID_CFA_KEY_MGMT 162

#define	RT_AHCI_ATA_ID_CFA_MODES 163

#define	RT_AHCI_ATA_ID_DATA_SET_MGMT 169

#define	RT_AHCI_ATA_ID_SCT_CMD_XPORT 206

#define	RT_AHCI_ATA_ID_ROT_SPEED 217

#define	RT_AHCI_ATA_ID_PIO4 (1 << 1)

#define	RT_AHCI_ATA_ID_SERNO_LEN 20

#define	RT_AHCI_ATA_ID_FW_REV_LEN 8

#define	RT_AHCI_ATA_ID_PROD_LEN 40

#define	RT_AHCI_ATA_ID_WWN_LEN 8

#define	RT_AHCI_ATA_CMD_DSM 0x06

#define	RT_AHCI_ATA_CMD_DEV_RESET 0x08 /* ATAPI device reset */

#define	RT_AHCI_ATA_CMD_PIO_READ 0x20 /* Read sectors with retry */

#define	RT_AHCI_ATA_CMD_PIO_READ_EXT 0x24

#define	RT_AHCI_ATA_CMD_READ_EXT 0x25

#define	RT_AHCI_ATA_CMD_READ_NATIVE_MAX_EXT 0x27

#define	RT_AHCI_ATA_CMD_READ_MULTI_EXT 0x29

#define	RT_AHCI_ATA_CMD_READ_LOG_EXT 0x2f

#define	RT_AHCI_ATA_CMD_PIO_WRITE 0x30 /* Write sectors with retry */

#define	RT_AHCI_ATA_CMD_PIO_WRITE_EXT 0x34

#define	RT_AHCI_ATA_CMD_WRITE_EXT 0x35

#define	RT_AHCI_ATA_CMD_SET_MAX_EXT 0x37

#define	RT_AHCI_ATA_CMD_WRITE_MULTI_EXT 0x39

#define	RT_AHCI_ATA_CMD_WRITE_FUA_EXT 0x3d

#define	RT_AHCI_ATA_CMD_VERIFY 0x40 /* Read verify sectors with retry */

#define	RT_AHCI_ATA_CMD_VERIFY_EXT 0x42

#define	RT_AHCI_ATA_CMD_FPDMA_READ 0x60

#define	RT_AHCI_ATA_CMD_FPDMA_WRITE 0x61

#define	RT_AHCI_ATA_CMD_EDD 0x90 /* Execute device diagnostic */

#define	RT_AHCI_ATA_CMD_INIT_DEV_PARAMS 0x91 /* Initialize device parameters */

#define	RT_AHCI_ATA_CMD_PACKET 0xa0 /* ATAPI packet */

#define	RT_AHCI_ATA_CMD_ID_ATAPI 0xa1 /* ATAPI identify device */

#define	RT_AHCI_ATA_CMD_CONF_OVERLAY 0xb1

#define	RT_AHCI_ATA_CMD_READ_MULTI 0xc4 /* Read multiple */

#define	RT_AHCI_ATA_CMD_WRITE_MULTI 0xc5 /* Write multiple */

#define	RT_AHCI_ATA_CMD_SET_MULTI 0xc6 /* Set multiple mode */

#define	RT_AHCI_ATA_CMD_READ 0xc8 /* Read DMA with retry */

#define	RT_AHCI_ATA_CMD_WRITE 0xca /* Write DMA with retry */

#define	RT_AHCI_ATA_CMD_WRITE_MULTI_FUA_EXT 0xce

#define	RT_AHCI_ATA_CMD_STANDBYNOW1 0xe0 /* Standby immediate */

#define	RT_AHCI_ATA_CMD_IDLEIMMEDIATE 0xe1 /* Idle immediate */

#define	RT_AHCI_ATA_CMD_STANDBY 0xe2 /* Place in standby power mode */

#define	RT_AHCI_ATA_CMD_IDLE 0xe3 /* Place in idle power mode */

#define	RT_AHCI_ATA_CMD_PMP_READ 0xe4 /* Read buffer */

#define	RT_AHCI_ATA_CMD_CHK_POWER 0xe5 /* Check power mode */

#define	RT_AHCI_ATA_CMD_SLEEP 0xe6 /* Sleep */

#define	RT_AHCI_ATA_CMD_FLUSH 0xe7

#define	RT_AHCI_ATA_CMD_PMP_WRITE 0xe8 /* Write buffer */

#define	RT_AHCI_ATA_CMD_FLUSH_EXT 0xea

#define	RT_AHCI_ATA_CMD_ID_ATA 0xec /* Identify device */

#define	RT_AHCI_ATA_CMD_SET_FEATURES 0xef /* Set features */

#define	RT_AHCI_ATA_CMD_SEC_FREEZE_LOCK 0xf5 /* Security freeze */

#define	RT_AHCI_ATA_CMD_READ_NATIVE_MAX 0xf8

#define	RT_AHCI_ATA_CMD_SET_MAX 0xf9

#define	RT_AHCI_ATA_DSM_TRIM 0x01

#define	RT_AHCI_ATA_PROT_FLAG_PIO RT_BIT(0)

#define	RT_AHCI_ATA_PROT_FLAG_DMA RT_BIT(1)

#define	RT_AHCI_ATA_PROT_FLAG_NCQ RT_BIT(2)

#define	RT_AHCI_ATA_PROT_FLAG_ATAPI RT_BIT(3)

#define	rt_ahci_ata_id_is_ata(id)

#define	rt_ahci_ata_id_has_lba(id)

#define	rt_ahci_ata_id_has_dma(id)

#define	rt_ahci_ata_id_has_ncq(id)

#define	rt_ahci_ata_id_queue_depth(id)

#define	rt_ahci_ata_id_removeable(id)

#define	rt_ahci_ata_id_iordy_disable(id)

#define	rt_ahci_ata_id_has_iordy(id)

#define	rt_ahci_ata_id_u32(id, n)

#define	rt_ahci_ata_id_u64(id, n)

函数
rt_inline rt_bool_t	rt_ahci_ata_id_has_lba48 (const rt_uint16_t *id)

rt_inline rt_uint64_t	rt_ahci_ata_id_n_sectors (rt_uint16_t *id)

rt_inline rt_bool_t	rt_ahci_ata_id_wcache_enabled (const rt_uint16_t *id)

rt_inline rt_bool_t	rt_ahci_ata_id_has_flush (const rt_uint16_t *id)

rt_inline rt_bool_t	rt_ahci_ata_id_has_flush_ext (const rt_uint16_t *id)

rt_err_t	rt_ahci_host_register (struct rt_ahci_host *host)

rt_err_t	rt_ahci_host_unregister (struct rt_ahci_host *host)

宏定义说明

◆ RT_AHCI_HBA_CAP

#define RT_AHCI_HBA_CAP 0x00 /* Host capability*/

在文件 ahci.h 第 22 行定义.

◆ RT_AHCI_CAP_NP

#define RT_AHCI_CAP_NP RT_GENMASK(4, 0) /* Number of Ports */

在文件 ahci.h 第 23 行定义.

◆ RT_AHCI_CAP_NCS

#define RT_AHCI_CAP_NCS RT_GENMASK(8, 12) /* Number of Command Slots */

在文件 ahci.h 第 24 行定义.

◆ RT_AHCI_CAP_PSC

#define RT_AHCI_CAP_PSC RT_BIT(13) /* Partial State Capable */

在文件 ahci.h 第 25 行定义.

◆ RT_AHCI_CAP_SSC

#define RT_AHCI_CAP_SSC RT_BIT(14) /* Slumber capable */

在文件 ahci.h 第 26 行定义.

◆ RT_AHCI_CAP_PMD

#define RT_AHCI_CAP_PMD RT_BIT(15) /* PIO Multiple DRQ Block */

在文件 ahci.h 第 27 行定义.

◆ RT_AHCI_CAP_SPM

#define RT_AHCI_CAP_SPM RT_BIT(17) /* Port Multiplier */

在文件 ahci.h 第 28 行定义.

◆ RT_AHCI_CAP_AHCI

#define RT_AHCI_CAP_AHCI RT_BIT(18) /* AHCI only */

在文件 ahci.h 第 29 行定义.

◆ RT_AHCI_CAP_SNZO

#define RT_AHCI_CAP_SNZO RT_BIT(19) /* Non-Zero DMA Offsets */

在文件 ahci.h 第 30 行定义.

◆ RT_AHCI_CAP_ISS

#define RT_AHCI_CAP_ISS RT_GENMASK(23, 20) /* Interface Speed Support */

在文件 ahci.h 第 31 行定义.

◆ RT_AHCI_CAP_CLO

#define RT_AHCI_CAP_CLO RT_BIT(24) /* Command List Override support */

在文件 ahci.h 第 32 行定义.

◆ RT_AHCI_CAP_SAL

#define RT_AHCI_CAP_SAL RT_BIT(25) /* Activity LED */

在文件 ahci.h 第 33 行定义.

◆ RT_AHCI_CAP_SALP

#define RT_AHCI_CAP_SALP RT_BIT(26) /* Aggressive Link Power Management */

在文件 ahci.h 第 34 行定义.

◆ RT_AHCI_CAP_SSS

#define RT_AHCI_CAP_SSS RT_BIT(27) /* Staggered Spin-up */

在文件 ahci.h 第 35 行定义.

◆ RT_AHCI_CAP_SIS

#define RT_AHCI_CAP_SIS RT_BIT(28) /* Interlock Switch */

在文件 ahci.h 第 36 行定义.

◆ RT_AHCI_CAP_NCQ

#define RT_AHCI_CAP_NCQ RT_BIT(30) /* Native Command Queueing */

在文件 ahci.h 第 37 行定义.

◆ RT_AHCI_CAP_64

#define RT_AHCI_CAP_64 RT_BIT(31) /* PCI DAC (64-bit DMA) support */

在文件 ahci.h 第 38 行定义.

◆ RT_AHCI_HBA_GHC

#define RT_AHCI_HBA_GHC 0x04 /* Global host control */

在文件 ahci.h 第 39 行定义.

◆ RT_AHCI_GHC_RESET

#define RT_AHCI_GHC_RESET RT_BIT(0) /* Reset controller; self-clear */

在文件 ahci.h 第 40 行定义.

◆ RT_AHCI_GHC_IRQ_EN

#define RT_AHCI_GHC_IRQ_EN RT_BIT(1) /* Global IRQ enable */

在文件 ahci.h 第 41 行定义.

◆ RT_AHCI_GHC_AHCI_EN

#define RT_AHCI_GHC_AHCI_EN RT_BIT(31) /* AHCI enabled */

在文件 ahci.h 第 42 行定义.

◆ RT_AHCI_HBA_INTS

#define RT_AHCI_HBA_INTS 0x08 /* Interrupt status */

在文件 ahci.h 第 43 行定义.

◆ RT_AHCI_HBA_PI

#define RT_AHCI_HBA_PI 0x0c /* Port implemented */

在文件 ahci.h 第 44 行定义.

◆ RT_AHCI_HBA_VS

#define RT_AHCI_HBA_VS 0x10 /* Version */

在文件 ahci.h 第 45 行定义.

◆ RT_AHCI_HBA_CCC_CTL

#define RT_AHCI_HBA_CCC_CTL 0x14 /* Command completion coalescing control */

在文件 ahci.h 第 46 行定义.

◆ RT_AHCI_HBA_CCC_PTS

#define RT_AHCI_HBA_CCC_PTS 0x18 /* Command completion coalescing ports */

在文件 ahci.h 第 47 行定义.

◆ RT_AHCI_HBA_EM_LOC

#define RT_AHCI_HBA_EM_LOC 0x1c /* Enclosure management location */

在文件 ahci.h 第 48 行定义.

◆ RT_AHCI_HBA_EM_CTL

#define RT_AHCI_HBA_EM_CTL 0x20 /* Enclosure management control */

在文件 ahci.h 第 49 行定义.

◆ RT_AHCI_HBA_CAP2

#define RT_AHCI_HBA_CAP2 0x24 /* Host capabilities extended */

在文件 ahci.h 第 50 行定义.

◆ RT_AHCI_HBA_BOHC

#define RT_AHCI_HBA_BOHC 0x28 /* BIOS/OS handoff control and status */

在文件 ahci.h 第 51 行定义.

◆ RT_AHCI_HBA_VENDOR

#define RT_AHCI_HBA_VENDOR 0xa0 /* Vendor specific registers (0xa0 - 0xff) */

在文件 ahci.h 第 52 行定义.

◆ RT_AHCI_PORT_CLB

#define RT_AHCI_PORT_CLB 0x00 /* Command list base address, 1K-byte aligned */

在文件 ahci.h 第 54 行定义.

◆ RT_AHCI_PORT_CLBU

#define RT_AHCI_PORT_CLBU 0x04 /* Command list base address upper 32 bits */

在文件 ahci.h 第 55 行定义.

◆ RT_AHCI_PORT_FB

#define RT_AHCI_PORT_FB 0x08 /* FIS base address, 256-byte aligned */

在文件 ahci.h 第 56 行定义.

◆ RT_AHCI_PORT_FBU

#define RT_AHCI_PORT_FBU 0x0C /* FIS base address upper 32 bits */

在文件 ahci.h 第 57 行定义.

◆ RT_AHCI_PORT_INTS

#define RT_AHCI_PORT_INTS 0x10 /* Interrupt status */

在文件 ahci.h 第 58 行定义.

◆ RT_AHCI_PORT_INTE

#define RT_AHCI_PORT_INTE 0x14 /* Interrupt enable */

在文件 ahci.h 第 59 行定义.

◆ RT_AHCI_PORT_INTE_D2H_REG_FIS

#define RT_AHCI_PORT_INTE_D2H_REG_FIS RT_BIT(0) /* D2H Register FIS rx'd */

在文件 ahci.h 第 60 行定义.

◆ RT_AHCI_PORT_INTE_PIOS_FIS

#define RT_AHCI_PORT_INTE_PIOS_FIS RT_BIT(1) /* PIO Setup FIS rx'd */

在文件 ahci.h 第 61 行定义.

◆ RT_AHCI_PORT_INTE_DMAS_FIS

#define RT_AHCI_PORT_INTE_DMAS_FIS RT_BIT(2) /* DMA Setup FIS rx'd */

在文件 ahci.h 第 62 行定义.

◆ RT_AHCI_PORT_INTE_SDB_FIS

#define RT_AHCI_PORT_INTE_SDB_FIS RT_BIT(3) /* Set Device Bits FIS rx'd */

在文件 ahci.h 第 63 行定义.

◆ RT_AHCI_PORT_INTE_UNK_FIS

#define RT_AHCI_PORT_INTE_UNK_FIS RT_BIT(4) /* Unknown FIS rx'd */

在文件 ahci.h 第 64 行定义.

◆ RT_AHCI_PORT_INTE_SG_DONE

#define RT_AHCI_PORT_INTE_SG_DONE RT_BIT(5) /* Descriptor processed */

在文件 ahci.h 第 65 行定义.

◆ RT_AHCI_PORT_INTE_CONNECT

#define RT_AHCI_PORT_INTE_CONNECT RT_BIT(6) /* Port connect change status */

在文件 ahci.h 第 66 行定义.

◆ RT_AHCI_PORT_INTE_DMPS

#define RT_AHCI_PORT_INTE_DMPS RT_BIT(7) /* Mechanical presence status */

在文件 ahci.h 第 67 行定义.

◆ RT_AHCI_PORT_INTE_PHYRDY

#define RT_AHCI_PORT_INTE_PHYRDY RT_BIT(22) /* PhyRdy changed */

在文件 ahci.h 第 68 行定义.

◆ RT_AHCI_PORT_INTE_BAD_PMP

#define RT_AHCI_PORT_INTE_BAD_PMP RT_BIT(23) /* Incorrect port multiplier */

在文件 ahci.h 第 69 行定义.

◆ RT_AHCI_PORT_INTE_OVERFLOW

#define RT_AHCI_PORT_INTE_OVERFLOW RT_BIT(24) /* Xfer exhausted available S/G */

在文件 ahci.h 第 70 行定义.

◆ RT_AHCI_PORT_INTE_IF_NONFATAL

#define RT_AHCI_PORT_INTE_IF_NONFATAL RT_BIT(26) /* Interface non-fatal error */

在文件 ahci.h 第 71 行定义.

◆ RT_AHCI_PORT_INTE_IF_ERR

#define RT_AHCI_PORT_INTE_IF_ERR RT_BIT(27) /* Interface fatal error */

在文件 ahci.h 第 72 行定义.

◆ RT_AHCI_PORT_INTE_HBUS_DATA_ERR

#define RT_AHCI_PORT_INTE_HBUS_DATA_ERR RT_BIT(28) /* Host bus data error */

在文件 ahci.h 第 73 行定义.

◆ RT_AHCI_PORT_INTE_HBUS_ERR

#define RT_AHCI_PORT_INTE_HBUS_ERR RT_BIT(29) /* Host bus fatal error */

在文件 ahci.h 第 74 行定义.

◆ RT_AHCI_PORT_INTE_TF_ERR

#define RT_AHCI_PORT_INTE_TF_ERR RT_BIT(30) /* Task file error */

在文件 ahci.h 第 75 行定义.

◆ RT_AHCI_PORT_INTE_COLD_PRES

#define RT_AHCI_PORT_INTE_COLD_PRES RT_BIT(31) /* Cold presence detect */

在文件 ahci.h 第 76 行定义.

◆ RT_AHCI_PORT_CMD

#define RT_AHCI_PORT_CMD 0x18 /* Command and status */

在文件 ahci.h 第 77 行定义.

◆ RT_AHCI_PORT_CMD_START

#define RT_AHCI_PORT_CMD_START RT_BIT(0) /* Enable port DMA engine */

在文件 ahci.h 第 78 行定义.

◆ RT_AHCI_PORT_CMD_SPIN_UP

#define RT_AHCI_PORT_CMD_SPIN_UP RT_BIT(1) /* Spin up device */

在文件 ahci.h 第 79 行定义.

◆ RT_AHCI_PORT_CMD_POWER_ON

#define RT_AHCI_PORT_CMD_POWER_ON RT_BIT(2) /* Power up device */

在文件 ahci.h 第 80 行定义.

◆ RT_AHCI_PORT_CMD_CLO

#define RT_AHCI_PORT_CMD_CLO RT_BIT(3) /* Command list override */

在文件 ahci.h 第 81 行定义.

◆ RT_AHCI_PORT_CMD_FIS_RX

#define RT_AHCI_PORT_CMD_FIS_RX RT_BIT(4) /* Enable FIS receive DMA engine */

在文件 ahci.h 第 82 行定义.

◆ RT_AHCI_PORT_CMD_FIS_ON

#define RT_AHCI_PORT_CMD_FIS_ON RT_BIT(14) /* FIS DMA engine running */

在文件 ahci.h 第 83 行定义.

◆ RT_AHCI_PORT_CMD_LIST_ON

#define RT_AHCI_PORT_CMD_LIST_ON RT_BIT(15) /* cmd list DMA engine running */

在文件 ahci.h 第 84 行定义.

◆ RT_AHCI_PORT_CMD_ATAPI

#define RT_AHCI_PORT_CMD_ATAPI RT_BIT(24) /* Device is ATAPI */

在文件 ahci.h 第 85 行定义.

◆ RT_AHCI_PORT_CMD_ACTIVE

#define RT_AHCI_PORT_CMD_ACTIVE RT_BIT(28) /* Active state */

在文件 ahci.h 第 86 行定义.

◆ RT_AHCI_PORT_TFD

#define RT_AHCI_PORT_TFD 0x20 /* Task file data */

在文件 ahci.h 第 87 行定义.

◆ RT_AHCI_PORT_TFDATA_ERR

#define RT_AHCI_PORT_TFDATA_ERR RT_BIT(0) /* Indicates an error during the transfer */

在文件 ahci.h 第 88 行定义.

◆ RT_AHCI_PORT_TFDATA_DRQ

#define RT_AHCI_PORT_TFDATA_DRQ RT_BIT(3) /* Indicates a data transfer is requested */

在文件 ahci.h 第 89 行定义.

◆ RT_AHCI_PORT_TFDATA_BSY

#define RT_AHCI_PORT_TFDATA_BSY RT_BIT(7) /* Indicates the interface is busy */

在文件 ahci.h 第 90 行定义.

◆ RT_AHCI_PORT_SIG

#define RT_AHCI_PORT_SIG 0x24 /* Signature */

在文件 ahci.h 第 91 行定义.

◆ RT_AHCI_PORT_SIG_REG_MASK

#define RT_AHCI_PORT_SIG_REG_MASK 0xff

在文件 ahci.h 第 92 行定义.

◆ RT_AHCI_PORT_SIG_SECTOR_NR_SHIFT

#define RT_AHCI_PORT_SIG_SECTOR_NR_SHIFT 0 /* Sector Count Register */

在文件 ahci.h 第 93 行定义.

◆ RT_AHCI_PORT_SIG_LBA_LOW_SHIFT

#define RT_AHCI_PORT_SIG_LBA_LOW_SHIFT 8 /* LBA Low Register */

在文件 ahci.h 第 94 行定义.

◆ RT_AHCI_PORT_SIG_LBA_MID_SHIFT

#define RT_AHCI_PORT_SIG_LBA_MID_SHIFT 16 /* LBA Mid Register */

在文件 ahci.h 第 95 行定义.

◆ RT_AHCI_PORT_SIG_LBA_HIGH_SHIFT

#define RT_AHCI_PORT_SIG_LBA_HIGH_SHIFT 24 /* LBA High Register */

在文件 ahci.h 第 96 行定义.

◆ RT_AHCI_PORT_SIG_SATA_CDROM

#define RT_AHCI_PORT_SIG_SATA_CDROM 0xeb140101

在文件 ahci.h 第 97 行定义.

◆ RT_AHCI_PORT_SIG_SATA_DISK

#define RT_AHCI_PORT_SIG_SATA_DISK 0x00000101

在文件 ahci.h 第 98 行定义.

◆ RT_AHCI_PORT_SSTS

#define RT_AHCI_PORT_SSTS 0x28 /* SATA status (SCR0:SStatus) */

在文件 ahci.h 第 99 行定义.

◆ RT_AHCI_PORT_SSTS_DET_MASK

#define RT_AHCI_PORT_SSTS_DET_MASK 0x3

在文件 ahci.h 第 100 行定义.

◆ RT_AHCI_PORT_SSTS_DET_COMINIT

#define RT_AHCI_PORT_SSTS_DET_COMINIT 0x1

在文件 ahci.h 第 101 行定义.

◆ RT_AHCI_PORT_SSTS_DET_PHYRDY

#define RT_AHCI_PORT_SSTS_DET_PHYRDY 0x3

在文件 ahci.h 第 102 行定义.

◆ RT_AHCI_PORT_SCTL

#define RT_AHCI_PORT_SCTL 0x2c /* SATA control (SCR2:SControl) */

在文件 ahci.h 第 103 行定义.

◆ RT_AHCI_PORT_SERR

#define RT_AHCI_PORT_SERR 0x30 /* SATA error (SCR1:SError) */

在文件 ahci.h 第 104 行定义.

◆ RT_AHCI_PORT_SERR_ERR_I

#define RT_AHCI_PORT_SERR_ERR_I RT_BIT(0) /* Recovered Data Integrity Error */

在文件 ahci.h 第 105 行定义.

◆ RT_AHCI_PORT_SERR_ERR_M

#define RT_AHCI_PORT_SERR_ERR_M RT_BIT(1) /* Recovered Communications Error */

在文件 ahci.h 第 106 行定义.

◆ RT_AHCI_PORT_SERR_ERR_T

#define RT_AHCI_PORT_SERR_ERR_T RT_BIT(8) /* Transient Data Integrity Error */

在文件 ahci.h 第 107 行定义.

◆ RT_AHCI_PORT_SERR_ERR_C

#define RT_AHCI_PORT_SERR_ERR_C RT_BIT(9) /* Persistent Communication or Data Integrity Error */

在文件 ahci.h 第 108 行定义.

◆ RT_AHCI_PORT_SERR_ERR_P

#define RT_AHCI_PORT_SERR_ERR_P RT_BIT(10) /* Protocol Error */

在文件 ahci.h 第 109 行定义.

◆ RT_AHCI_PORT_SERR_ERR_E

#define RT_AHCI_PORT_SERR_ERR_E RT_BIT(11) /* Internal Error */

在文件 ahci.h 第 110 行定义.

◆ RT_AHCI_PORT_SERR_DIAG_N

#define RT_AHCI_PORT_SERR_DIAG_N RT_BIT(16) /* PhyRdy Change */

在文件 ahci.h 第 111 行定义.

◆ RT_AHCI_PORT_SERR_DIAG_I

#define RT_AHCI_PORT_SERR_DIAG_I RT_BIT(17) /* Phy Internal Error */

在文件 ahci.h 第 112 行定义.

◆ RT_AHCI_PORT_SERR_DIAG_W

#define RT_AHCI_PORT_SERR_DIAG_W RT_BIT(18) /* Comm Wake */

在文件 ahci.h 第 113 行定义.

◆ RT_AHCI_PORT_SERR_DIAG_B

#define RT_AHCI_PORT_SERR_DIAG_B RT_BIT(19) /* 10B to 8B Decode Error */

在文件 ahci.h 第 114 行定义.

◆ RT_AHCI_PORT_SERR_DIAG_D

#define RT_AHCI_PORT_SERR_DIAG_D RT_BIT(20) /* Disparity Error */

在文件 ahci.h 第 115 行定义.

◆ RT_AHCI_PORT_SERR_DIAG_C

#define RT_AHCI_PORT_SERR_DIAG_C RT_BIT(21) /* CRC Error */

在文件 ahci.h 第 116 行定义.

◆ RT_AHCI_PORT_SERR_DIAG_H

#define RT_AHCI_PORT_SERR_DIAG_H RT_BIT(22) /* Handshake Error */

在文件 ahci.h 第 117 行定义.

◆ RT_AHCI_PORT_SERR_DIAG_S

#define RT_AHCI_PORT_SERR_DIAG_S RT_BIT(23) /* Link Sequence Error */

在文件 ahci.h 第 118 行定义.

◆ RT_AHCI_PORT_SERR_DIAG_T

#define RT_AHCI_PORT_SERR_DIAG_T RT_BIT(24) /* Transport state transition error */

在文件 ahci.h 第 119 行定义.

◆ RT_AHCI_PORT_SERR_DIAG_F

#define RT_AHCI_PORT_SERR_DIAG_F RT_BIT(25) /* Unknown FIS Type */

在文件 ahci.h 第 120 行定义.

◆ RT_AHCI_PORT_SERR_DIAG_X

#define RT_AHCI_PORT_SERR_DIAG_X RT_BIT(26) /* Exchanged */

在文件 ahci.h 第 121 行定义.

◆ RT_AHCI_PORT_SACT

#define RT_AHCI_PORT_SACT 0x34 /* SATA active (SCR3:SActive) */

在文件 ahci.h 第 122 行定义.

◆ RT_AHCI_PORT_CI

#define RT_AHCI_PORT_CI 0x38 /* Command issue */

在文件 ahci.h 第 123 行定义.

◆ RT_AHCI_PORT_SNTF

#define RT_AHCI_PORT_SNTF 0x3c /* SATA notification (SCR4:SNotification) */

在文件 ahci.h 第 124 行定义.

◆ RT_AHCI_PORT_FBS

#define RT_AHCI_PORT_FBS 0x40 /* FIS-based switch control */

在文件 ahci.h 第 125 行定义.

◆ RT_AHCI_PORT_VENDOR

#define RT_AHCI_PORT_VENDOR 0x70 /* Vendor specific (0x70 - 0x7f) */

在文件 ahci.h 第 126 行定义.

◆ RT_AHCI_MAX_SG

#define RT_AHCI_MAX_SG 56

在文件 ahci.h 第 128 行定义.

◆ RT_AHCI_CMD_SLOT_SIZE

#define RT_AHCI_CMD_SLOT_SIZE 32

在文件 ahci.h 第 129 行定义.

◆ RT_AHCI_MAX_CMD_SLOT

#define RT_AHCI_MAX_CMD_SLOT 32

在文件 ahci.h 第 130 行定义.

◆ RT_AHCI_RX_FIS_SIZE

#define RT_AHCI_RX_FIS_SIZE 256

在文件 ahci.h 第 131 行定义.

◆ RT_AHCI_CMD_TBL_HDR

#define RT_AHCI_CMD_TBL_HDR 0x80

在文件 ahci.h 第 132 行定义.

◆ RT_AHCI_CMD_TBL_CDB

#define RT_AHCI_CMD_TBL_CDB 0x40

在文件 ahci.h 第 133 行定义.

◆ RT_AHCI_CMD_TBL_SIZE

#define RT_AHCI_CMD_TBL_SIZE RT_AHCI_CMD_TBL_HDR + (RT_AHCI_MAX_SG * 16)

在文件 ahci.h 第 134 行定义.

◆ RT_AHCI_DMA_SIZE

#define RT_AHCI_DMA_SIZE (RT_AHCI_CMD_SLOT_SIZE * RT_AHCI_MAX_CMD_SLOT + RT_AHCI_CMD_TBL_SIZE + RT_AHCI_RX_FIS_SIZE)

在文件 ahci.h 第 135 行定义.

◆ RT_ACHI_PRDT_BYTES_MAX

#define RT_ACHI_PRDT_BYTES_MAX (4 * 1024 * 1024)

在文件 ahci.h 第 136 行定义.

◆ RT_AHCI_FIS_TYPE_REG_H2D

#define RT_AHCI_FIS_TYPE_REG_H2D 0x27 /* Register FIS - host to device */

在文件 ahci.h 第 138 行定义.

◆ RT_AHCI_FIS_TYPE_REG_D2H

#define RT_AHCI_FIS_TYPE_REG_D2H 0x34 /* Register FIS - device to host */

在文件 ahci.h 第 139 行定义.

◆ RT_AHCI_FIS_TYPE_DMA_ACT

#define RT_AHCI_FIS_TYPE_DMA_ACT 0x39 /* DMA activate FIS - device to host */

在文件 ahci.h 第 140 行定义.

◆ RT_AHCI_FIS_TYPE_DMA_SETUP

#define RT_AHCI_FIS_TYPE_DMA_SETUP 0x41 /* DMA setup FIS - bidirectional */

在文件 ahci.h 第 141 行定义.

◆ RT_AHCI_FIS_TYPE_DATA

#define RT_AHCI_FIS_TYPE_DATA 0x46 /* Data FIS - bidirectional */

在文件 ahci.h 第 142 行定义.

◆ RT_AHCI_FIS_TYPE_BIST

#define RT_AHCI_FIS_TYPE_BIST 0x58 /* BIST activate FIS - bidirectional */

在文件 ahci.h 第 143 行定义.

◆ RT_AHCI_FIS_TYPE_PIO_SETUP

#define RT_AHCI_FIS_TYPE_PIO_SETUP 0x5f /* PIO setup FIS - device to host */

在文件 ahci.h 第 144 行定义.

◆ RT_AHCI_FIS_TYPE_DEV_BITS

#define RT_AHCI_FIS_TYPE_DEV_BITS 0xa1 /* Set device bits FIS - device to host */

在文件 ahci.h 第 145 行定义.

◆ RT_AHCI_ATA_ID_WORDS

#define RT_AHCI_ATA_ID_WORDS 256

在文件 ahci.h 第 147 行定义.

◆ RT_AHCI_ATA_ID_CONFIG

#define RT_AHCI_ATA_ID_CONFIG 0

在文件 ahci.h 第 148 行定义.

◆ RT_AHCI_ATA_ID_CYLS

#define RT_AHCI_ATA_ID_CYLS 1

在文件 ahci.h 第 149 行定义.

◆ RT_AHCI_ATA_ID_HEADS

#define RT_AHCI_ATA_ID_HEADS 3

在文件 ahci.h 第 150 行定义.

◆ RT_AHCI_ATA_ID_SECTORS

#define RT_AHCI_ATA_ID_SECTORS 6

在文件 ahci.h 第 151 行定义.

◆ RT_AHCI_ATA_ID_SERNO

#define RT_AHCI_ATA_ID_SERNO 10

在文件 ahci.h 第 152 行定义.

◆ RT_AHCI_ATA_ID_BUF_SIZE

#define RT_AHCI_ATA_ID_BUF_SIZE 21

在文件 ahci.h 第 153 行定义.

◆ RT_AHCI_ATA_ID_FW_REV

#define RT_AHCI_ATA_ID_FW_REV 23

在文件 ahci.h 第 154 行定义.

◆ RT_AHCI_ATA_ID_PROD

#define RT_AHCI_ATA_ID_PROD 27

在文件 ahci.h 第 155 行定义.

◆ RT_AHCI_ATA_ID_MAX_MULTSECT

#define RT_AHCI_ATA_ID_MAX_MULTSECT 47

在文件 ahci.h 第 156 行定义.

◆ RT_AHCI_ATA_ID_DWORD_IO

#define RT_AHCI_ATA_ID_DWORD_IO 48

在文件 ahci.h 第 157 行定义.

◆ RT_AHCI_ATA_ID_TRUSTED

#define RT_AHCI_ATA_ID_TRUSTED 48

在文件 ahci.h 第 158 行定义.

◆ RT_AHCI_ATA_ID_CAPABILITY

#define RT_AHCI_ATA_ID_CAPABILITY 49

在文件 ahci.h 第 159 行定义.

◆ RT_AHCI_ATA_ID_OLD_PIO_MODES

#define RT_AHCI_ATA_ID_OLD_PIO_MODES 51

在文件 ahci.h 第 160 行定义.

◆ RT_AHCI_ATA_ID_OLD_DMA_MODES

#define RT_AHCI_ATA_ID_OLD_DMA_MODES 52

在文件 ahci.h 第 161 行定义.

◆ RT_AHCI_ATA_ID_FIELD_VALID

#define RT_AHCI_ATA_ID_FIELD_VALID 53

在文件 ahci.h 第 162 行定义.

◆ RT_AHCI_ATA_ID_CUR_CYLS

#define RT_AHCI_ATA_ID_CUR_CYLS 54

在文件 ahci.h 第 163 行定义.

◆ RT_AHCI_ATA_ID_CUR_HEADS

#define RT_AHCI_ATA_ID_CUR_HEADS 55

在文件 ahci.h 第 164 行定义.

◆ RT_AHCI_ATA_ID_CUR_SECTORS

#define RT_AHCI_ATA_ID_CUR_SECTORS 56

在文件 ahci.h 第 165 行定义.

◆ RT_AHCI_ATA_ID_MULTSECT

#define RT_AHCI_ATA_ID_MULTSECT 59

在文件 ahci.h 第 166 行定义.

◆ RT_AHCI_ATA_ID_LBA_CAPACITY

#define RT_AHCI_ATA_ID_LBA_CAPACITY 60

在文件 ahci.h 第 167 行定义.

◆ RT_AHCI_ATA_ID_SWDMA_MODES

#define RT_AHCI_ATA_ID_SWDMA_MODES 62

在文件 ahci.h 第 168 行定义.

◆ RT_AHCI_ATA_ID_MWDMA_MODES

#define RT_AHCI_ATA_ID_MWDMA_MODES 63

在文件 ahci.h 第 169 行定义.

◆ RT_AHCI_ATA_ID_PIO_MODES

#define RT_AHCI_ATA_ID_PIO_MODES 64

在文件 ahci.h 第 170 行定义.

◆ RT_AHCI_ATA_ID_EIDE_DMA_MIN

#define RT_AHCI_ATA_ID_EIDE_DMA_MIN 65

在文件 ahci.h 第 171 行定义.

◆ RT_AHCI_ATA_ID_EIDE_DMA_TIME

#define RT_AHCI_ATA_ID_EIDE_DMA_TIME 66

在文件 ahci.h 第 172 行定义.

◆ RT_AHCI_ATA_ID_EIDE_PIO

#define RT_AHCI_ATA_ID_EIDE_PIO 67

在文件 ahci.h 第 173 行定义.

◆ RT_AHCI_ATA_ID_EIDE_PIO_IORDY

#define RT_AHCI_ATA_ID_EIDE_PIO_IORDY 68

在文件 ahci.h 第 174 行定义.

◆ RT_AHCI_ATA_ID_ADDITIONAL_SUPP

#define RT_AHCI_ATA_ID_ADDITIONAL_SUPP 69

在文件 ahci.h 第 175 行定义.

◆ RT_AHCI_ATA_ID_QUEUE_DEPTH

#define RT_AHCI_ATA_ID_QUEUE_DEPTH 75

在文件 ahci.h 第 176 行定义.

◆ RT_AHCI_ATA_ID_SATA_CAPABILITY

#define RT_AHCI_ATA_ID_SATA_CAPABILITY 76

在文件 ahci.h 第 177 行定义.

◆ RT_AHCI_ATA_ID_SATA_CAPABILITY_2

#define RT_AHCI_ATA_ID_SATA_CAPABILITY_2 77

在文件 ahci.h 第 178 行定义.

◆ RT_AHCI_ATA_ID_FEATURE_SUPP

#define RT_AHCI_ATA_ID_FEATURE_SUPP 78

在文件 ahci.h 第 179 行定义.

◆ RT_AHCI_ATA_ID_MAJOR_VER

#define RT_AHCI_ATA_ID_MAJOR_VER 80

在文件 ahci.h 第 180 行定义.

◆ RT_AHCI_ATA_ID_COMMAND_SET_1

#define RT_AHCI_ATA_ID_COMMAND_SET_1 82

在文件 ahci.h 第 181 行定义.

◆ RT_AHCI_ATA_ID_COMMAND_SET_2

#define RT_AHCI_ATA_ID_COMMAND_SET_2 83

在文件 ahci.h 第 182 行定义.

◆ RT_AHCI_ATA_ID_CFSSE

#define RT_AHCI_ATA_ID_CFSSE 84

在文件 ahci.h 第 183 行定义.

◆ RT_AHCI_ATA_ID_CFS_ENABLE_1

#define RT_AHCI_ATA_ID_CFS_ENABLE_1 85

在文件 ahci.h 第 184 行定义.

◆ RT_AHCI_ATA_ID_CFS_ENABLE_2

#define RT_AHCI_ATA_ID_CFS_ENABLE_2 86

在文件 ahci.h 第 185 行定义.

◆ RT_AHCI_ATA_ID_CSF_DEFAULT

#define RT_AHCI_ATA_ID_CSF_DEFAULT 87

在文件 ahci.h 第 186 行定义.

◆ RT_AHCI_ATA_ID_UDMA_MODES

#define RT_AHCI_ATA_ID_UDMA_MODES 88

在文件 ahci.h 第 187 行定义.

◆ RT_AHCI_ATA_ID_HW_CONFIG

#define RT_AHCI_ATA_ID_HW_CONFIG 93

在文件 ahci.h 第 188 行定义.

◆ RT_AHCI_ATA_ID_SPG

#define RT_AHCI_ATA_ID_SPG 98

在文件 ahci.h 第 189 行定义.

◆ RT_AHCI_ATA_ID_LBA_CAPACITY_2

#define RT_AHCI_ATA_ID_LBA_CAPACITY_2 100

在文件 ahci.h 第 190 行定义.

◆ RT_AHCI_ATA_ID_SECTOR_SIZE

#define RT_AHCI_ATA_ID_SECTOR_SIZE 106

在文件 ahci.h 第 191 行定义.

◆ RT_AHCI_ATA_ID_WWN

#define RT_AHCI_ATA_ID_WWN 108

在文件 ahci.h 第 192 行定义.

◆ RT_AHCI_ATA_ID_LOGICAL_SECTOR_SIZE

#define RT_AHCI_ATA_ID_LOGICAL_SECTOR_SIZE 117

在文件 ahci.h 第 193 行定义.

◆ RT_AHCI_ATA_ID_COMMAND_SET_3

#define RT_AHCI_ATA_ID_COMMAND_SET_3 119

在文件 ahci.h 第 194 行定义.

◆ RT_AHCI_ATA_ID_COMMAND_SET_4

#define RT_AHCI_ATA_ID_COMMAND_SET_4 120

在文件 ahci.h 第 195 行定义.

◆ RT_AHCI_ATA_ID_LAST_LUN

#define RT_AHCI_ATA_ID_LAST_LUN 126

在文件 ahci.h 第 196 行定义.

◆ RT_AHCI_ATA_ID_DLF

#define RT_AHCI_ATA_ID_DLF 128

在文件 ahci.h 第 197 行定义.

◆ RT_AHCI_ATA_ID_CSFO

#define RT_AHCI_ATA_ID_CSFO 129

在文件 ahci.h 第 198 行定义.

◆ RT_AHCI_ATA_ID_CFA_POWER

#define RT_AHCI_ATA_ID_CFA_POWER 160

在文件 ahci.h 第 199 行定义.

◆ RT_AHCI_ATA_ID_CFA_KEY_MGMT

#define RT_AHCI_ATA_ID_CFA_KEY_MGMT 162

在文件 ahci.h 第 200 行定义.

◆ RT_AHCI_ATA_ID_CFA_MODES

#define RT_AHCI_ATA_ID_CFA_MODES 163

在文件 ahci.h 第 201 行定义.

◆ RT_AHCI_ATA_ID_DATA_SET_MGMT

#define RT_AHCI_ATA_ID_DATA_SET_MGMT 169

在文件 ahci.h 第 202 行定义.

◆ RT_AHCI_ATA_ID_SCT_CMD_XPORT

#define RT_AHCI_ATA_ID_SCT_CMD_XPORT 206

在文件 ahci.h 第 203 行定义.

◆ RT_AHCI_ATA_ID_ROT_SPEED

#define RT_AHCI_ATA_ID_ROT_SPEED 217

在文件 ahci.h 第 204 行定义.

◆ RT_AHCI_ATA_ID_PIO4

#define RT_AHCI_ATA_ID_PIO4 (1 << 1)

在文件 ahci.h 第 205 行定义.

◆ RT_AHCI_ATA_ID_SERNO_LEN

#define RT_AHCI_ATA_ID_SERNO_LEN 20

在文件 ahci.h 第 206 行定义.

◆ RT_AHCI_ATA_ID_FW_REV_LEN

#define RT_AHCI_ATA_ID_FW_REV_LEN 8

在文件 ahci.h 第 207 行定义.

◆ RT_AHCI_ATA_ID_PROD_LEN

#define RT_AHCI_ATA_ID_PROD_LEN 40

在文件 ahci.h 第 208 行定义.

◆ RT_AHCI_ATA_ID_WWN_LEN

#define RT_AHCI_ATA_ID_WWN_LEN 8

在文件 ahci.h 第 209 行定义.

◆ RT_AHCI_ATA_CMD_DSM

#define RT_AHCI_ATA_CMD_DSM 0x06

在文件 ahci.h 第 211 行定义.

◆ RT_AHCI_ATA_CMD_DEV_RESET

#define RT_AHCI_ATA_CMD_DEV_RESET 0x08 /* ATAPI device reset */

在文件 ahci.h 第 212 行定义.

◆ RT_AHCI_ATA_CMD_PIO_READ

#define RT_AHCI_ATA_CMD_PIO_READ 0x20 /* Read sectors with retry */

在文件 ahci.h 第 213 行定义.

◆ RT_AHCI_ATA_CMD_PIO_READ_EXT

#define RT_AHCI_ATA_CMD_PIO_READ_EXT 0x24

在文件 ahci.h 第 214 行定义.

◆ RT_AHCI_ATA_CMD_READ_EXT

#define RT_AHCI_ATA_CMD_READ_EXT 0x25

在文件 ahci.h 第 215 行定义.

◆ RT_AHCI_ATA_CMD_READ_NATIVE_MAX_EXT

#define RT_AHCI_ATA_CMD_READ_NATIVE_MAX_EXT 0x27

在文件 ahci.h 第 216 行定义.

◆ RT_AHCI_ATA_CMD_READ_MULTI_EXT

#define RT_AHCI_ATA_CMD_READ_MULTI_EXT 0x29

在文件 ahci.h 第 217 行定义.

◆ RT_AHCI_ATA_CMD_READ_LOG_EXT

#define RT_AHCI_ATA_CMD_READ_LOG_EXT 0x2f

在文件 ahci.h 第 218 行定义.

◆ RT_AHCI_ATA_CMD_PIO_WRITE

#define RT_AHCI_ATA_CMD_PIO_WRITE 0x30 /* Write sectors with retry */

在文件 ahci.h 第 219 行定义.

◆ RT_AHCI_ATA_CMD_PIO_WRITE_EXT

#define RT_AHCI_ATA_CMD_PIO_WRITE_EXT 0x34

在文件 ahci.h 第 220 行定义.

◆ RT_AHCI_ATA_CMD_WRITE_EXT

#define RT_AHCI_ATA_CMD_WRITE_EXT 0x35

在文件 ahci.h 第 221 行定义.

◆ RT_AHCI_ATA_CMD_SET_MAX_EXT

#define RT_AHCI_ATA_CMD_SET_MAX_EXT 0x37

在文件 ahci.h 第 222 行定义.

◆ RT_AHCI_ATA_CMD_WRITE_MULTI_EXT

#define RT_AHCI_ATA_CMD_WRITE_MULTI_EXT 0x39

在文件 ahci.h 第 223 行定义.

◆ RT_AHCI_ATA_CMD_WRITE_FUA_EXT

#define RT_AHCI_ATA_CMD_WRITE_FUA_EXT 0x3d

在文件 ahci.h 第 224 行定义.

◆ RT_AHCI_ATA_CMD_VERIFY

#define RT_AHCI_ATA_CMD_VERIFY 0x40 /* Read verify sectors with retry */

在文件 ahci.h 第 225 行定义.

◆ RT_AHCI_ATA_CMD_VERIFY_EXT

#define RT_AHCI_ATA_CMD_VERIFY_EXT 0x42

在文件 ahci.h 第 226 行定义.

◆ RT_AHCI_ATA_CMD_FPDMA_READ

#define RT_AHCI_ATA_CMD_FPDMA_READ 0x60

在文件 ahci.h 第 227 行定义.

◆ RT_AHCI_ATA_CMD_FPDMA_WRITE

#define RT_AHCI_ATA_CMD_FPDMA_WRITE 0x61

在文件 ahci.h 第 228 行定义.

◆ RT_AHCI_ATA_CMD_EDD

#define RT_AHCI_ATA_CMD_EDD 0x90 /* Execute device diagnostic */

在文件 ahci.h 第 229 行定义.

◆ RT_AHCI_ATA_CMD_INIT_DEV_PARAMS

#define RT_AHCI_ATA_CMD_INIT_DEV_PARAMS 0x91 /* Initialize device parameters */

在文件 ahci.h 第 230 行定义.

◆ RT_AHCI_ATA_CMD_PACKET

#define RT_AHCI_ATA_CMD_PACKET 0xa0 /* ATAPI packet */

在文件 ahci.h 第 231 行定义.

◆ RT_AHCI_ATA_CMD_ID_ATAPI

#define RT_AHCI_ATA_CMD_ID_ATAPI 0xa1 /* ATAPI identify device */

在文件 ahci.h 第 232 行定义.

◆ RT_AHCI_ATA_CMD_CONF_OVERLAY

#define RT_AHCI_ATA_CMD_CONF_OVERLAY 0xb1

在文件 ahci.h 第 233 行定义.

◆ RT_AHCI_ATA_CMD_READ_MULTI

#define RT_AHCI_ATA_CMD_READ_MULTI 0xc4 /* Read multiple */

在文件 ahci.h 第 234 行定义.

◆ RT_AHCI_ATA_CMD_WRITE_MULTI

#define RT_AHCI_ATA_CMD_WRITE_MULTI 0xc5 /* Write multiple */

在文件 ahci.h 第 235 行定义.

◆ RT_AHCI_ATA_CMD_SET_MULTI

#define RT_AHCI_ATA_CMD_SET_MULTI 0xc6 /* Set multiple mode */

在文件 ahci.h 第 236 行定义.

◆ RT_AHCI_ATA_CMD_READ

#define RT_AHCI_ATA_CMD_READ 0xc8 /* Read DMA with retry */

在文件 ahci.h 第 237 行定义.

◆ RT_AHCI_ATA_CMD_WRITE

#define RT_AHCI_ATA_CMD_WRITE 0xca /* Write DMA with retry */

在文件 ahci.h 第 238 行定义.

◆ RT_AHCI_ATA_CMD_WRITE_MULTI_FUA_EXT

#define RT_AHCI_ATA_CMD_WRITE_MULTI_FUA_EXT 0xce

在文件 ahci.h 第 239 行定义.

◆ RT_AHCI_ATA_CMD_STANDBYNOW1

#define RT_AHCI_ATA_CMD_STANDBYNOW1 0xe0 /* Standby immediate */

在文件 ahci.h 第 240 行定义.

◆ RT_AHCI_ATA_CMD_IDLEIMMEDIATE

#define RT_AHCI_ATA_CMD_IDLEIMMEDIATE 0xe1 /* Idle immediate */

在文件 ahci.h 第 241 行定义.

◆ RT_AHCI_ATA_CMD_STANDBY

#define RT_AHCI_ATA_CMD_STANDBY 0xe2 /* Place in standby power mode */

在文件 ahci.h 第 242 行定义.

◆ RT_AHCI_ATA_CMD_IDLE

#define RT_AHCI_ATA_CMD_IDLE 0xe3 /* Place in idle power mode */

在文件 ahci.h 第 243 行定义.

◆ RT_AHCI_ATA_CMD_PMP_READ

#define RT_AHCI_ATA_CMD_PMP_READ 0xe4 /* Read buffer */

在文件 ahci.h 第 244 行定义.

◆ RT_AHCI_ATA_CMD_CHK_POWER

#define RT_AHCI_ATA_CMD_CHK_POWER 0xe5 /* Check power mode */

在文件 ahci.h 第 245 行定义.

◆ RT_AHCI_ATA_CMD_SLEEP

#define RT_AHCI_ATA_CMD_SLEEP 0xe6 /* Sleep */

在文件 ahci.h 第 246 行定义.

◆ RT_AHCI_ATA_CMD_FLUSH

#define RT_AHCI_ATA_CMD_FLUSH 0xe7

在文件 ahci.h 第 247 行定义.

◆ RT_AHCI_ATA_CMD_PMP_WRITE

#define RT_AHCI_ATA_CMD_PMP_WRITE 0xe8 /* Write buffer */

在文件 ahci.h 第 248 行定义.

◆ RT_AHCI_ATA_CMD_FLUSH_EXT

#define RT_AHCI_ATA_CMD_FLUSH_EXT 0xea

在文件 ahci.h 第 249 行定义.

◆ RT_AHCI_ATA_CMD_ID_ATA

#define RT_AHCI_ATA_CMD_ID_ATA 0xec /* Identify device */

在文件 ahci.h 第 250 行定义.

◆ RT_AHCI_ATA_CMD_SET_FEATURES

#define RT_AHCI_ATA_CMD_SET_FEATURES 0xef /* Set features */

在文件 ahci.h 第 251 行定义.

◆ RT_AHCI_ATA_CMD_SEC_FREEZE_LOCK

#define RT_AHCI_ATA_CMD_SEC_FREEZE_LOCK 0xf5 /* Security freeze */

在文件 ahci.h 第 252 行定义.

◆ RT_AHCI_ATA_CMD_READ_NATIVE_MAX

#define RT_AHCI_ATA_CMD_READ_NATIVE_MAX 0xf8

在文件 ahci.h 第 253 行定义.

◆ RT_AHCI_ATA_CMD_SET_MAX

#define RT_AHCI_ATA_CMD_SET_MAX 0xf9

在文件 ahci.h 第 254 行定义.

◆ RT_AHCI_ATA_DSM_TRIM

#define RT_AHCI_ATA_DSM_TRIM 0x01

在文件 ahci.h 第 256 行定义.

◆ RT_AHCI_ATA_PROT_FLAG_PIO

#define RT_AHCI_ATA_PROT_FLAG_PIO RT_BIT(0)

在文件 ahci.h 第 258 行定义.

◆ RT_AHCI_ATA_PROT_FLAG_DMA

#define RT_AHCI_ATA_PROT_FLAG_DMA RT_BIT(1)

在文件 ahci.h 第 259 行定义.

◆ RT_AHCI_ATA_PROT_FLAG_NCQ

#define RT_AHCI_ATA_PROT_FLAG_NCQ RT_BIT(2)

在文件 ahci.h 第 260 行定义.

◆ RT_AHCI_ATA_PROT_FLAG_ATAPI

#define RT_AHCI_ATA_PROT_FLAG_ATAPI RT_BIT(3)

在文件 ahci.h 第 261 行定义.

◆ rt_ahci_ata_id_is_ata

#define rt_ahci_ata_id_is_ata ( id )

值:

(((id)[0] & (1 << 15)) == 0)

在文件 ahci.h 第 263 行定义.

◆ rt_ahci_ata_id_has_lba

#define rt_ahci_ata_id_has_lba ( id )

值:

((id)[49] & (1 << 9))

在文件 ahci.h 第 264 行定义.

◆ rt_ahci_ata_id_has_dma

#define rt_ahci_ata_id_has_dma ( id )

值:

((id)[49] & (1 << 8))

在文件 ahci.h 第 265 行定义.

◆ rt_ahci_ata_id_has_ncq

#define rt_ahci_ata_id_has_ncq ( id )

值:

((id)[76] & (1 << 8))

在文件 ahci.h 第 266 行定义.

◆ rt_ahci_ata_id_queue_depth

#define rt_ahci_ata_id_queue_depth ( id )

值:

(((id)[75] & 0x1f) + 1)

在文件 ahci.h 第 267 行定义.

◆ rt_ahci_ata_id_removeable

#define rt_ahci_ata_id_removeable ( id )

值:

((id)[0] & (1 << 7))

在文件 ahci.h 第 268 行定义.

◆ rt_ahci_ata_id_iordy_disable

#define rt_ahci_ata_id_iordy_disable ( id )

值:

((id)[49] & (1 << 10))

在文件 ahci.h 第 269 行定义.

◆ rt_ahci_ata_id_has_iordy

#define rt_ahci_ata_id_has_iordy ( id )

值:

((id)[49] & (1 << 11))

在文件 ahci.h 第 270 行定义.

◆ rt_ahci_ata_id_u32

#define rt_ahci_ata_id_u32	(		id,
			n )

值:

(((rt_uint32_t)(id)[(n) + 1] << 16) | ((rt_uint32_t) (id)[(n)]))

rt_uint32_t

unsigned int rt_uint32_t

定义 rttypes.h:53

在文件 ahci.h 第 272 行定义.

◆ rt_ahci_ata_id_u64

#define rt_ahci_ata_id_u64	(		id,
			n )

值:

(((rt_uint64_t)(id)[(n) + 3] << 48) | ((rt_uint64_t)(id)[(n) + 2] << 32) | \

((rt_uint64_t)(id)[(n) + 1] << 16) | ((rt_uint64_t)(id)[(n) + 0]) )

rt_uint64_t

unsigned long long rt_uint64_t

定义 rttypes.h:59

在文件 ahci.h 第 273 行定义.

273#define rt_ahci_ata_id_u64(id, n) (((rt_uint64_t)(id)[(n) + 3] << 48) | ((rt_uint64_t)(id)[(n) + 2] << 32) | \

274 ((rt_uint64_t)(id)[(n) + 1] << 16) | ((rt_uint64_t)(id)[(n) + 0]) )

函数说明

◆ rt_ahci_ata_id_has_lba48()

rt_inline rt_bool_t rt_ahci_ata_id_has_lba48 ( const rt_uint16_t * id )

在文件 ahci.h 第 276 行定义.

{
    if ((id[RT_AHCI_ATA_ID_COMMAND_SET_2] & 0xc000) != 0x4000 ||
        !rt_ahci_ata_id_u64(id, RT_AHCI_ATA_ID_LBA_CAPACITY_2))
    {
        return 0;
    }
 
    return !!(id[RT_AHCI_ATA_ID_COMMAND_SET_2] & (1 << 10));
}

引用了 RT_AHCI_ATA_ID_COMMAND_SET_2, RT_AHCI_ATA_ID_LBA_CAPACITY_2 , 以及 rt_ahci_ata_id_u64.

这是这个函数的调用关系图:

◆ rt_ahci_ata_id_n_sectors()

rt_inline rt_uint64_t rt_ahci_ata_id_n_sectors ( rt_uint16_t * id )

在文件 ahci.h 第 287 行定义.

{
    if (rt_ahci_ata_id_has_lba(id))
    {
        if (rt_ahci_ata_id_has_lba48(id))
        {
            return rt_ahci_ata_id_u64(id, RT_AHCI_ATA_ID_LBA_CAPACITY_2);
        }
 
        return rt_ahci_ata_id_u32(id, RT_AHCI_ATA_ID_LBA_CAPACITY);
    }
 
    return 0;
}

引用了 rt_ahci_ata_id_has_lba, rt_ahci_ata_id_has_lba48(), RT_AHCI_ATA_ID_LBA_CAPACITY, RT_AHCI_ATA_ID_LBA_CAPACITY_2, rt_ahci_ata_id_u32 , 以及 rt_ahci_ata_id_u64.

函数调用图:

◆ rt_ahci_ata_id_wcache_enabled()

rt_inline rt_bool_t rt_ahci_ata_id_wcache_enabled ( const rt_uint16_t * id )

在文件 ahci.h 第 302 行定义.

{
    if ((id[RT_AHCI_ATA_ID_CSF_DEFAULT] & 0xc000) != 0x4000)
    {
        return RT_FALSE;
    }
    return id[RT_AHCI_ATA_ID_CFS_ENABLE_1] & (1 << 5);
}

引用了 RT_AHCI_ATA_ID_CFS_ENABLE_1, RT_AHCI_ATA_ID_CSF_DEFAULT , 以及 RT_FALSE.

◆ rt_ahci_ata_id_has_flush()

rt_inline rt_bool_t rt_ahci_ata_id_has_flush ( const rt_uint16_t * id )

在文件 ahci.h 第 311 行定义.

{
    if ((id[RT_AHCI_ATA_ID_COMMAND_SET_2] & 0xc000) != 0x4000)
    {
        return RT_FALSE;
    }
    return id[RT_AHCI_ATA_ID_COMMAND_SET_2] & (1 << 12);
}

引用了 RT_AHCI_ATA_ID_COMMAND_SET_2 , 以及 RT_FALSE.

◆ rt_ahci_ata_id_has_flush_ext()

rt_inline rt_bool_t rt_ahci_ata_id_has_flush_ext ( const rt_uint16_t * id )

在文件 ahci.h 第 320 行定义.

{
    if ((id[RT_AHCI_ATA_ID_COMMAND_SET_2] & 0xc000) != 0x4000)
    {
        return RT_FALSE;
    }
    return id[RT_AHCI_ATA_ID_COMMAND_SET_2] & (1 << 13);
}